Lines Matching defs:mode
114 * bits 28-31: related to single stage mode? (bit 8/12)
117 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_clock)
133 /* NM2 == 0 is used to determine single stage mode on two stage plls */
175 nv_crtc_dpms(struct drm_crtc *crtc, int mode)
183 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode,
186 if (nv_crtc->last_dpms == mode) /* Don't do unnecessary mode changes. */
189 nv_crtc->last_dpms = mode;
197 switch (mode) {
237 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
245 int horizDisplay = (mode->crtc_hdisplay >> 3) - 1;
246 int horizStart = (mode->crtc_hsync_start >> 3) + 1;
247 int horizEnd = (mode->crtc_hsync_end >> 3) + 1;
248 int horizTotal = (mode->crtc_htotal >> 3) - 5;
249 int horizBlankStart = (mode->crtc_hdisplay >> 3) - 1;
250 int horizBlankEnd = (mode->crtc_htotal >> 3) - 1;
251 int vertDisplay = mode->crtc_vdisplay - 1;
252 int vertStart = mode->crtc_vsync_start - 1;
253 int vertEnd = mode->crtc_vsync_end - 1;
254 int vertTotal = mode->crtc_vtotal - 2;
255 int vertBlankStart = mode->crtc_vdisplay - 1;
256 int vertBlankEnd = mode->crtc_vtotal - 1;
284 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
305 if ((mode->flags & (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))
306 && (mode->flags & (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) {
309 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
311 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
314 int vdisplay = mode->vdisplay;
315 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
317 if (mode->vscan > 1)
318 vdisplay *= mode->vscan;
334 if (mode->flags & DRM_MODE_FLAG_CLKDIV2)
363 regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL_HT_SCANDBL) : 0) |
392 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
408 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
423 regp->Graphics[NV_VIO_GX_MODE_INDEX] = 0x40; /* 256 color mode */
424 regp->Graphics[NV_VIO_GX_MISC_INDEX] = 0x05; /* map 64k mem + graphic mode */
444 regp->Attribute[NV_CIO_AR_MODE_INDEX] = 0x01; /* Enable graphic mode */
453 * Sets up registers for the given mode/adjusted_mode pair.
461 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode)
490 /* Registers not directly related to the (s)vga mode */
515 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
557 regp->crtc_830 = mode->crtc_vdisplay - 3;
558 regp->crtc_834 = mode->crtc_vdisplay - 1;
579 /* Enable slaved mode (called MODE_TV in nv4ref.h) */
597 regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
629 * Sets up registers for the given mode/adjusted_mode pair.
637 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode,
646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
661 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock);
887 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8,
949 * NPM mode needs NV_PCRTC_CURSOR_CONFIG_ALPHA_BLEND set and is what the
950 * blob uses, however we get given PM cursors so we use PM mode