Lines Matching defs:index
57 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index)
59 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index,
60 crtcstate->CRTC[index]);
67 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
82 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
88 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634);
125 struct nv04_crtc_reg *regp = &state->crtc_reg[nv_crtc->index];
129 if (nvbios_pll_parse(bios, nv_crtc->index ? PLL_VPLL1 : PLL_VPLL0,
162 state->pllsel |= nv_crtc->index ? PLLSEL_VPLL2_MASK : PLLSEL_VPLL1_MASK;
184 nv_crtc->index);
192 NVSetOwner(dev, nv_crtc->index);
195 crtc1A = NVReadVgaCrtc(dev, nv_crtc->index,
224 NVVgaSeqReset(dev, nv_crtc->index, true);
226 seq1 |= (NVReadVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX) & ~0x20);
227 NVWriteVgaSeq(dev, nv_crtc->index, NV_VIO_SR_CLOCK_INDEX, seq1);
228 crtc17 |= (NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX) & ~0x80);
230 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CR_MODE_INDEX, crtc17);
231 NVVgaSeqReset(dev, nv_crtc->index, false);
233 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RPC1_INDEX, crtc1A);
241 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
466 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
467 struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
498 if (nv_crtc->index == 0)
504 if (pPriv->overlayCRTC == nv_crtc->index)
541 if (nv_crtc->index == 0)
547 if (!nv_crtc->index)
620 if (disp->image[nv_crtc->index])
621 nouveau_bo_unpin(disp->image[nv_crtc->index]);
622 nouveau_bo_ref(nvbo, &disp->image[nv_crtc->index]);
646 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index);
654 nv_lock_vga_crtc_shadow(dev, nv_crtc->index, -1);
670 struct nv04_crtc_reg *crtc_state = &state->crtc_reg[nv_crtc->index];
672 struct nv04_crtc_reg *crtc_saved = &saved->crtc_reg[nv_crtc->index];
675 NVSetOwner(crtc->dev, nv_crtc->index);
677 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved);
690 int head = nv_crtc->index;
710 NVSetOwner(dev, nv_crtc->index);
715 NVBlankScreen(dev, nv_crtc->index, true);
718 NVWriteCRTC(dev, nv_crtc->index, NV_PCRTC_CONFIG, NV_PCRTC_CONFIG_START_ADDRESS_NON_VGA);
720 uint32_t reg900 = NVReadRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900);
721 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_900, reg900 & ~0x10000);
731 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
737 uint8_t tmp = NVReadVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR);
739 NVWriteVgaCrtc(dev, nv_crtc->index, NV_CIO_CRE_RCR, tmp);
757 if (disp->image[nv_crtc->index])
758 nouveau_bo_unpin(disp->image[nv_crtc->index]);
759 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
778 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC;
789 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg);
797 if (disp->image[nv_crtc->index])
798 nouveau_bo_unpin(disp->image[nv_crtc->index]);
799 nouveau_bo_ref(NULL, &disp->image[nv_crtc->index]);
832 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
837 NV_DEBUG(drm, "index %d\n", nv_crtc->index);
869 NVWriteRAMDAC(dev, nv_crtc->index, NV_PRAMDAC_GENERAL_CONTROL,
884 nv_set_crtc_base(dev, nv_crtc->index, regp->fb_start);
1154 int head = nouveau_crtc(crtc)->index;
1298 nv_crtc->index = crtc_num;
1337 ret = nvif_head_ctor(&disp->disp, nv_crtc->base.name, nv_crtc->index, &nv_crtc->head);