Lines Matching defs:mxsfb
5 * This code is based on drivers/video/fbdev/mxsfb.c :
41 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
43 return (val & mxsfb->devdata->hs_wdth_mask) <<
44 mxsfb->devdata->hs_wdth_shift;
51 static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb,
54 struct drm_device *drm = mxsfb->drm;
55 const u32 format = mxsfb->crtc.primary->state->fb->format->format;
64 ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
96 writel(ctrl1, mxsfb->base + LCDC_CTRL1);
97 writel(ctrl, mxsfb->base + LCDC_CTRL);
100 static void mxsfb_set_mode(struct mxsfb_drm_private *mxsfb, u32 bus_flags)
102 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode;
107 mxsfb->base + mxsfb->devdata->transfer_count);
131 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
134 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
138 writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
140 mxsfb->base + LCDC_VDCTRL2);
144 mxsfb->base + LCDC_VDCTRL3);
147 mxsfb->base + LCDC_VDCTRL4);
151 static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
155 if (mxsfb->clk_disp_axi)
156 clk_prepare_enable(mxsfb->clk_disp_axi);
157 clk_prepare_enable(mxsfb->clk);
160 if (mxsfb->devdata->has_ctrl2) {
161 reg = readl(mxsfb->base + LCDC_V4_CTRL2);
164 writel(reg, mxsfb->base + LCDC_V4_CTRL2);
168 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
171 reg = readl(mxsfb->base + LCDC_VDCTRL4);
173 writel(reg, mxsfb->base + LCDC_VDCTRL4);
200 reg = readl(mxsfb->base + LCDC_CTRL1);
202 writel(reg, mxsfb->base + LCDC_CTRL1);
204 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
207 static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
215 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
217 readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
220 reg = readl(mxsfb->base + LCDC_VDCTRL4);
222 writel(reg, mxsfb->base + LCDC_VDCTRL4);
224 clk_disable_unprepare(mxsfb->clk);
225 if (mxsfb->clk_disp_axi)
226 clk_disable_unprepare(mxsfb->clk_disp_axi);
242 static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb)
252 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
256 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR);
258 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
262 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE);
267 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
268 readl(mxsfb->base + LCDC_CTRL1);
269 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
270 readl(mxsfb->base + LCDC_CTRL1);
272 if (mxsfb->devdata->has_overlay)
273 writel(0, mxsfb->base + LCDC_AS_CTRL);
278 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb,
282 struct drm_device *drm = mxsfb->crtc.dev;
283 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode;
284 u32 bus_flags = mxsfb->connector->display_info.bus_flags;
287 if (mxsfb->bridge && mxsfb->bridge->timings)
288 bus_flags = mxsfb->bridge->timings->input_bus_flags;
294 (int)(clk_get_rate(mxsfb->clk) / 1000));
300 err = mxsfb_reset_block(mxsfb);
304 mxsfb_set_formats(mxsfb, bus_format);
306 clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
308 mxsfb_set_mode(mxsfb, bus_flags);
349 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
353 struct drm_device *drm = mxsfb->drm;
358 mxsfb_enable_axi_clk(mxsfb);
363 if (mxsfb->bridge) {
366 mxsfb->bridge);
381 if (!bus_format && mxsfb->connector->display_info.num_bus_formats)
382 bus_format = mxsfb->connector->display_info.bus_formats[0];
388 mxsfb_crtc_mode_set_nofb(mxsfb, bridge_state, bus_format);
393 writel(dma_addr, mxsfb->base + mxsfb->devdata->cur_buf);
394 writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
397 mxsfb_enable_controller(mxsfb);
403 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
404 struct drm_device *drm = mxsfb->drm;
407 mxsfb_disable_controller(mxsfb);
419 mxsfb_disable_axi_clk(mxsfb);
425 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
428 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
429 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
436 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
439 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
440 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
445 struct mxsfb_drm_private *mxsfb;
450 mxsfb = to_mxsfb_drm_private(crtc->dev);
453 mxsfb->crc_active = true;
455 mxsfb->crc_active = false;
526 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
530 &mxsfb->crtc);
541 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
548 writel(dma_addr, mxsfb->base + mxsfb->devdata->next_buf);
556 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
564 writel(0, mxsfb->base + LCDC_AS_CTRL);
576 writel(dma_addr, mxsfb->base + LCDC_AS_NEXT_BUF);
583 writel(dma_addr, mxsfb->base + LCDC_AS_BUF);
611 writel(ctrl, mxsfb->base + LCDC_AS_CTRL);
617 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
619 writel(0, mxsfb->base + LCDC_AS_CTRL);
674 int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb)
676 struct drm_encoder *encoder = &mxsfb->encoder;
677 struct drm_crtc *crtc = &mxsfb->crtc;
680 drm_plane_helper_add(&mxsfb->planes.primary,
682 ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1,
691 if (mxsfb->devdata->has_overlay) {
692 drm_plane_helper_add(&mxsfb->planes.overlay,
694 ret = drm_universal_plane_init(mxsfb->drm,
695 &mxsfb->planes.overlay, 1,
706 if (mxsfb->devdata->has_crc32) {
707 ret = drm_crtc_init_with_planes(mxsfb->drm, crtc,
708 &mxsfb->planes.primary, NULL,
712 ret = drm_crtc_init_with_planes(mxsfb->drm, crtc,
713 &mxsfb->planes.primary, NULL,
720 return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs,