Lines Matching defs:base
35 struct drm_crtc_state base; /* always be the first member */
43 return container_of(s, struct lcdif_crtc_state, base);
173 lcdif->base + LCDC_V8_DISP_PARA);
177 lcdif->base + LCDC_V8_DISP_PARA);
181 lcdif->base + LCDC_V8_DISP_PARA);
193 lcdif->base + LCDC_V8_CTRLDESCL0_5);
197 lcdif->base + LCDC_V8_CTRLDESCL0_5);
201 lcdif->base + LCDC_V8_CTRLDESCL0_5);
205 lcdif->base + LCDC_V8_CTRLDESCL0_5);
209 lcdif->base + LCDC_V8_CTRLDESCL0_5);
213 lcdif->base + LCDC_V8_CTRLDESCL0_5);
219 lcdif->base + LCDC_V8_CTRLDESCL0_5);
224 lcdif->base + LCDC_V8_CTRLDESCL0_5);
229 lcdif->base + LCDC_V8_CTRLDESCL0_5);
234 lcdif->base + LCDC_V8_CTRLDESCL0_5);
253 lcdif->base + LCDC_V8_CSC0_CTRL);
263 lcdif->base + LCDC_V8_CSC0_COEF0);
265 lcdif->base + LCDC_V8_CSC0_COEF1);
267 lcdif->base + LCDC_V8_CSC0_COEF2);
269 lcdif->base + LCDC_V8_CSC0_COEF3);
271 lcdif->base + LCDC_V8_CSC0_COEF4);
273 lcdif->base + LCDC_V8_CSC0_COEF5);
281 lcdif->base + LCDC_V8_CSC0_CTRL);
283 writel(coeffs[0], lcdif->base + LCDC_V8_CSC0_COEF0);
284 writel(coeffs[1], lcdif->base + LCDC_V8_CSC0_COEF1);
285 writel(coeffs[2], lcdif->base + LCDC_V8_CSC0_COEF2);
286 writel(coeffs[3], lcdif->base + LCDC_V8_CSC0_COEF3);
287 writel(coeffs[4], lcdif->base + LCDC_V8_CSC0_COEF4);
288 writel(coeffs[5], lcdif->base + LCDC_V8_CSC0_COEF5);
291 writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL);
309 writel(ctrl, lcdif->base + LCDC_V8_CTRL);
313 lcdif->base + LCDC_V8_DISP_SIZE);
317 lcdif->base + LCDC_V8_HSYN_PARA);
321 lcdif->base + LCDC_V8_VSYN_PARA);
325 lcdif->base + LCDC_V8_VSYN_HSYN_WIDTH);
329 lcdif->base + LCDC_V8_CTRLDESCL0_1);
342 writel(ctrl, lcdif->base + LCDC_V8_CTRLDESCL0_3);
352 lcdif->base + LCDC_V8_PANIC0_THRES);
359 lcdif->base + LCDC_V8_INT_ENABLE_D1);
361 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
363 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
365 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
367 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
375 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
377 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
379 ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5,
385 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
387 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
390 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D1);
395 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);
396 readl(lcdif->base + LCDC_V8_CTRL);
397 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);
398 readl(lcdif->base + LCDC_V8_CTRL);
471 encoder->base.id, encoder->name);
512 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
514 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
551 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
553 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
600 __drm_atomic_helper_crtc_reset(crtc, &state->base);
616 __drm_atomic_helper_crtc_duplicate_state(crtc, &new->base);
621 return &new->base;
629 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
630 writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0);
640 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0);
641 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
694 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
696 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);