Lines Matching refs:viu
119 line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7;
126 line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7;
166 priv->viu.osd1_afbcd = true;
168 priv->viu.osd1_afbcd = false;
171 priv->viu.osd1_ctrl_stat = OSD_ENABLE |
175 priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
181 priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
183 if (priv->viu.osd1_afbcd) {
186 priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR;
187 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE;
188 priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN;
189 priv->viu.osd1_ctrl_stat |= VIU_OSD1_CFG_SYN_EN;
193 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
194 priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD;
197 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
200 priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD;
205 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
207 if (priv->viu.osd1_afbcd &&
209 priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN |
216 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
221 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
225 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
229 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
239 priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN;
244 priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN;
294 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
296 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
298 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
301 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
303 priv->viu.osd_sc_i_wh_m1 = 0;
304 priv->viu.osd_sc_o_h_start_end = 0;
305 priv->viu.osd_sc_o_v_start_end = 0;
306 priv->viu.osd_sc_ctrl0 = 0;
311 priv->viu.osd_sc_v_ctrl0 =
318 priv->viu.osd_sc_v_ctrl0 |=
323 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
324 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
326 priv->viu.osd_sc_v_ctrl0 = 0;
327 priv->viu.osd_sc_v_phase_step = 0;
328 priv->viu.osd_sc_v_ini_phase = 0;
333 priv->viu.osd_sc_h_ctrl0 =
338 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
339 priv->viu.osd_sc_h_ini_phase = 0;
341 priv->viu.osd_sc_h_ctrl0 = 0;
342 priv->viu.osd_sc_h_phase_step = 0;
343 priv->viu.osd_sc_h_ini_phase = 0;
351 priv->viu.osd1_blk0_cfg[1] =
354 priv->viu.osd1_blk0_cfg[2] =
357 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
358 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
361 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
362 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
363 priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
364 priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
370 priv->viu.osd1_addr = gem->dma_addr;
371 priv->viu.osd1_stride = fb->pitches[0];
372 priv->viu.osd1_height = fb->height;
373 priv->viu.osd1_width = fb->width;
375 if (priv->viu.osd1_afbcd) {
381 priv->viu.osd1_blk2_cfg4 =
394 priv->viu.osd1_enabled = true;
419 priv->viu.osd1_enabled = false;