Lines Matching refs:dsi
223 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
225 u32 temp = readl(dsi->regs + offset);
227 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
230 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
233 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
234 struct mtk_phy_timing *timing = &dsi->phy_timing;
262 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
263 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
264 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
265 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
268 static void mtk_dsi_enable(struct mtk_dsi *dsi)
270 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
273 static void mtk_dsi_disable(struct mtk_dsi *dsi)
275 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
278 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
280 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
281 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
284 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
286 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
287 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
290 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
292 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
293 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
296 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
298 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
299 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
300 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
303 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
305 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
306 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
309 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
311 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
312 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
313 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
316 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
318 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
321 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
323 if (enter && !mtk_dsi_clk_hs_state(dsi))
324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
325 else if (!enter && mtk_dsi_clk_hs_state(dsi))
326 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
329 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
333 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
334 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
336 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
342 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
345 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
347 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
348 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
351 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
353 struct videomode *vm = &dsi->vm;
357 if (dsi->format == MIPI_DSI_FMT_RGB565)
365 switch (dsi->format) {
380 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
381 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
382 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
385 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
389 switch (dsi->lanes) {
407 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
410 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET)
413 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
416 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
421 switch (dsi->format) {
444 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
445 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
448 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
457 struct mtk_phy_timing *timing = &dsi->phy_timing;
459 struct videomode *vm = &dsi->vm;
461 if (dsi->format == MIPI_DSI_FMT_RGB565)
466 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
467 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
468 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
469 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
471 if (dsi->driver_data->has_size_ctl)
473 dsi->regs + DSI_SIZE_CON);
477 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
486 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
487 delta += dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET ? 0 : 2;
491 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
505 if ((dsi->mode_flags & MIPI_DSI_HS_PKT_END_ALIGNED) &&
506 (dsi->lanes == 4)) {
508 roundup(horizontal_sync_active_byte, dsi->lanes) - 2;
510 roundup(horizontal_frontporch_byte, dsi->lanes) - 2;
512 roundup(horizontal_backporch_byte, dsi->lanes) - 2;
514 (vm->hactive * dsi_tmp_buf_bpp + 2) % dsi->lanes;
517 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
518 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
519 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
521 mtk_dsi_ps_control(dsi);
524 static void mtk_dsi_start(struct mtk_dsi *dsi)
526 writel(0, dsi->regs + DSI_START);
527 writel(1, dsi->regs + DSI_START);
530 static void mtk_dsi_stop(struct mtk_dsi *dsi)
532 writel(0, dsi->regs + DSI_START);
535 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
537 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
540 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
544 writel(inten, dsi->regs + DSI_INTEN);
547 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
549 dsi->irq_data |= irq_bit;
552 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
554 dsi->irq_data &= ~irq_bit;
557 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
563 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
564 dsi->irq_data & irq_flag,
569 mtk_dsi_enable(dsi);
570 mtk_dsi_reset_engine(dsi);
578 struct mtk_dsi *dsi = dev_id;
582 status = readl(dsi->regs + DSI_INTSTA) & flag;
586 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
587 tmp = readl(dsi->regs + DSI_INTSTA);
590 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
591 mtk_dsi_irq_data_set(dsi, status);
592 wake_up_interruptible(&dsi->irq_wait_queue);
598 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
600 mtk_dsi_irq_data_clear(dsi, irq_flag);
601 mtk_dsi_set_cmd_mode(dsi);
603 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
611 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
613 struct device *dev = dsi->host.dev;
617 if (++dsi->refcount != 1)
620 switch (dsi->format) {
634 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
635 dsi->lanes);
637 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
643 phy_power_on(dsi->phy);
645 ret = clk_prepare_enable(dsi->engine_clk);
651 ret = clk_prepare_enable(dsi->digital_clk);
657 mtk_dsi_enable(dsi);
659 if (dsi->driver_data->has_shadow_ctl)
661 dsi->regs + DSI_SHADOW_DEBUG);
663 mtk_dsi_reset_engine(dsi);
664 mtk_dsi_phy_timconfig(dsi);
666 mtk_dsi_ps_control_vact(dsi);
667 mtk_dsi_set_vm_cmd(dsi);
668 mtk_dsi_config_vdo_timing(dsi);
669 mtk_dsi_set_interrupt_enable(dsi);
673 clk_disable_unprepare(dsi->engine_clk);
675 phy_power_off(dsi->phy);
677 dsi->refcount--;
681 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
683 if (WARN_ON(dsi->refcount == 0))
686 if (--dsi->refcount != 0)
694 * after dsi is fully set.
696 mtk_dsi_stop(dsi);
698 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
699 mtk_dsi_reset_engine(dsi);
700 mtk_dsi_lane0_ulp_mode_enter(dsi);
701 mtk_dsi_clk_ulp_mode_enter(dsi);
703 writel(0, dsi->regs + DSI_TXRX_CTRL);
705 mtk_dsi_disable(dsi);
707 clk_disable_unprepare(dsi->engine_clk);
708 clk_disable_unprepare(dsi->digital_clk);
710 phy_power_off(dsi->phy);
712 dsi->lanes_ready = false;
715 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
717 if (!dsi->lanes_ready) {
718 dsi->lanes_ready = true;
719 mtk_dsi_rxtx_control(dsi);
721 mtk_dsi_reset_dphy(dsi);
722 mtk_dsi_clk_ulp_mode_leave(dsi);
723 mtk_dsi_lane0_ulp_mode_leave(dsi);
724 mtk_dsi_clk_hs_mode(dsi, 0);
730 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
732 if (dsi->enabled)
735 mtk_dsi_lane_ready(dsi);
736 mtk_dsi_set_mode(dsi);
737 mtk_dsi_clk_hs_mode(dsi, 1);
739 mtk_dsi_start(dsi);
741 dsi->enabled = true;
744 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
746 if (!dsi->enabled)
749 dsi->enabled = false;
755 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
757 /* Attach the panel or bridge to the dsi bridge */
758 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
759 &dsi->bridge, flags);
766 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
768 drm_display_mode_to_videomode(adjusted, &dsi->vm);
774 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
776 mtk_output_dsi_disable(dsi);
782 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
784 if (dsi->refcount == 0)
787 mtk_output_dsi_enable(dsi);
793 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
796 ret = mtk_dsi_poweron(dsi);
798 DRM_ERROR("failed to power on dsi\n");
804 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
806 mtk_dsi_poweroff(dsi);
823 struct mtk_dsi *dsi = dev_get_drvdata(dev);
825 mtk_dsi_poweron(dsi);
830 struct mtk_dsi *dsi = dev_get_drvdata(dev);
832 mtk_dsi_poweroff(dsi);
835 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
839 ret = drm_simple_encoder_init(drm, &dsi->encoder,
846 dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->host.dev);
848 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
853 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
854 if (IS_ERR(dsi->connector)) {
856 ret = PTR_ERR(dsi->connector);
859 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
864 drm_encoder_cleanup(&dsi->encoder);
872 struct mtk_dsi *dsi = dev_get_drvdata(dev);
874 ret = mtk_dsi_encoder_init(drm, dsi);
884 struct mtk_dsi *dsi = dev_get_drvdata(dev);
886 drm_encoder_cleanup(&dsi->encoder);
897 struct mtk_dsi *dsi = host_to_dsi(host);
901 dsi->lanes = device->lanes;
902 dsi->format = device->format;
903 dsi->mode_flags = device->mode_flags;
904 dsi->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
905 if (IS_ERR(dsi->next_bridge))
906 return PTR_ERR(dsi->next_bridge);
908 drm_bridge_add(&dsi->bridge);
913 drm_bridge_remove(&dsi->bridge);
923 struct mtk_dsi *dsi = host_to_dsi(host);
926 drm_bridge_remove(&dsi->bridge);
930 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
935 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
938 DRM_WARN("polling dsi wait not busy timeout!\n");
940 mtk_dsi_enable(dsi);
941 mtk_dsi_reset_engine(dsi);
968 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
973 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
993 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
997 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
998 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
1001 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
1004 mtk_dsi_wait_for_idle(dsi);
1005 mtk_dsi_irq_data_clear(dsi, flag);
1006 mtk_dsi_cmdq(dsi, msg);
1007 mtk_dsi_start(dsi);
1009 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
1018 struct mtk_dsi *dsi = host_to_dsi(host);
1026 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
1028 mtk_dsi_stop(dsi);
1029 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
1037 mtk_dsi_lane_ready(dsi);
1039 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
1049 DRM_ERROR("dsi receive buffer size may be NULL\n");
1055 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
1073 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
1078 mtk_dsi_set_mode(dsi);
1079 mtk_dsi_start(dsi);
1093 struct mtk_dsi *dsi;
1099 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1100 if (!dsi)
1103 dsi->host.ops = &mtk_dsi_ops;
1104 dsi->host.dev = dev;
1105 ret = mipi_dsi_host_register(&dsi->host);
1111 dsi->driver_data = of_device_get_match_data(dev);
1113 dsi->engine_clk = devm_clk_get(dev, "engine");
1114 if (IS_ERR(dsi->engine_clk)) {
1115 ret = PTR_ERR(dsi->engine_clk);
1122 dsi->digital_clk = devm_clk_get(dev, "digital");
1123 if (IS_ERR(dsi->digital_clk)) {
1124 ret = PTR_ERR(dsi->digital_clk);
1131 dsi->hs_clk = devm_clk_get(dev, "hs");
1132 if (IS_ERR(dsi->hs_clk)) {
1133 ret = PTR_ERR(dsi->hs_clk);
1139 dsi->regs = devm_ioremap_resource(dev, regs);
1140 if (IS_ERR(dsi->regs)) {
1141 ret = PTR_ERR(dsi->regs);
1146 dsi->phy = devm_phy_get(dev, "dphy");
1147 if (IS_ERR(dsi->phy)) {
1148 ret = PTR_ERR(dsi->phy);
1160 IRQF_TRIGGER_NONE, dev_name(&pdev->dev), dsi);
1162 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1166 init_waitqueue_head(&dsi->irq_wait_queue);
1168 platform_set_drvdata(pdev, dsi);
1170 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1171 dsi->bridge.of_node = dev->of_node;
1172 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1177 mipi_dsi_host_unregister(&dsi->host);
1183 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1185 mtk_output_dsi_disable(dsi);
1186 mipi_dsi_host_unregister(&dsi->host);
1210 { .compatible = "mediatek,mt2701-dsi",
1212 { .compatible = "mediatek,mt8173-dsi",
1214 { .compatible = "mediatek,mt8183-dsi",
1216 { .compatible = "mediatek,mt8186-dsi",
1226 .name = "mtk-dsi",