Lines Matching refs:mcde
74 void mcde_display_irq(struct mcde *mcde)
80 mispp = readl(mcde->regs + MCDE_MISPP);
81 misovl = readl(mcde->regs + MCDE_MISOVL);
82 mischnl = readl(mcde->regs + MCDE_MISCHNL);
92 if (!mcde->dpi_output && mcde_dsi_irq(mcde->mdsi)) {
101 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
102 spin_lock(&mcde->flow_lock);
103 if (--mcde->flow_active == 0) {
104 dev_dbg(mcde->dev, "TE0 IRQ\n");
106 val = readl(mcde->regs + MCDE_CRA0);
108 writel(val, mcde->regs + MCDE_CRA0);
110 spin_unlock(&mcde->flow_lock);
116 dev_dbg(mcde->dev, "chnl A vblank IRQ\n");
120 dev_dbg(mcde->dev, "chnl B vblank IRQ\n");
124 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");
126 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");
128 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");
130 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");
131 writel(mispp, mcde->regs + MCDE_RISPP);
134 drm_crtc_handle_vblank(&mcde->pipe.crtc);
137 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);
138 writel(misovl, mcde->regs + MCDE_RISOVL);
141 dev_info(mcde->dev, "some stray channel error IRQ %08x\n",
143 writel(mischnl, mcde->regs + MCDE_RISCHNL);
146 void mcde_display_disable_irqs(struct mcde *mcde)
149 writel(0, mcde->regs + MCDE_IMSCPP);
150 writel(0, mcde->regs + MCDE_IMSCOVL);
151 writel(0, mcde->regs + MCDE_IMSCCHNL);
154 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
155 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);
156 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);
196 static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,
324 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
328 writel(val, mcde->regs + conf);
333 writel(val, mcde->regs + cr);
338 static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,
408 writel(val, mcde->regs + conf1);
432 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
460 dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",
463 writel(val, mcde->regs + conf2);
466 writel(mcde->stride, mcde->regs + ljinc);
468 writel(0, mcde->regs + crop);
480 writel(val, mcde->regs + cr);
487 writel(val, mcde->regs + comp);
490 static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,
533 switch (mcde->flow_mode) {
571 dev_err(mcde->dev, "unknown flow mode %d\n",
572 mcde->flow_mode);
576 writel(val, mcde->regs + sync);
581 writel(val, mcde->regs + conf);
589 writel(val, mcde->regs + stat);
590 writel(0, mcde->regs + bgcol);
596 mcde->regs + mux);
600 mcde->regs + mux);
608 if (mcde->dpi_output) {
612 dev_info(mcde->dev, "stripwidth: %d\n", stripwidth);
621 writel(val, mcde->regs + MCDE_SYNCHCONFA);
624 writel(val, mcde->regs + MCDE_SYNCHCONFB);
630 static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,
695 writel(val, mcde->regs + ctrl);
700 writel(val, mcde->regs + cr0);
702 spin_lock(&mcde->fifo_crx1_lock);
703 val = readl(mcde->regs + cr1);
708 if (mcde->dpi_output) {
709 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);
714 dev_info(mcde->dev, "panel does not specify bus format, assume RGB888\n");
734 dev_err(mcde->dev, "unknown bus format, assume RGB888\n");
744 writel(val, mcde->regs + cr1);
745 spin_unlock(&mcde->fifo_crx1_lock);
748 static void mcde_configure_dsi_formatter(struct mcde *mcde,
790 dev_err(mcde->dev, "tried to configure a non-DSI formatter as DSI\n");
799 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
801 switch (mcde->mdsi->format) {
811 dev_err(mcde->dev,
821 dev_err(mcde->dev, "unknown DSI format\n");
824 writel(val, mcde->regs + conf0);
826 writel(formatter_frame, mcde->regs + frame);
827 writel(pkt_size, mcde->regs + pkt);
828 writel(0, mcde->regs + sync);
834 writel(val, mcde->regs + cmdw);
840 writel(0, mcde->regs + delay0);
841 writel(0, mcde->regs + delay1);
844 static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)
857 dev_err(mcde->dev, "cannot enable FIFO %c\n",
862 spin_lock(&mcde->flow_lock);
863 val = readl(mcde->regs + cr);
865 writel(val, mcde->regs + cr);
866 mcde->flow_active++;
867 spin_unlock(&mcde->flow_lock);
870 static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,
885 dev_err(mcde->dev, "cannot disable FIFO %c\n",
890 spin_lock(&mcde->flow_lock);
891 val = readl(mcde->regs + cr);
893 writel(val, mcde->regs + cr);
894 mcde->flow_active = 0;
895 spin_unlock(&mcde->flow_lock);
901 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {
904 dev_err(mcde->dev,
915 static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,
946 val = readl(mcde->regs + ctrl);
948 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");
950 mcde_enable_fifo(mcde, fifo);
952 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);
954 mcde_disable_fifo(mcde, fifo, true);
973 static void mcde_setup_dpi(struct mcde *mcde, const struct drm_display_mode *mode,
976 struct drm_connector *connector = drm_panel_bridge_connector(mcde->bridge);
989 dev_info(mcde->dev, "output on DPI LCD from channel A\n");
991 dev_info(mcde->dev, "HSW: %d, HFP: %d, HBP: %d, VSW: %d, VFP: %d, VBP: %d\n",
1027 writel(val, mcde->regs + MCDE_CONF0);
1030 writel(0, mcde->regs + MCDE_TVCRA);
1035 writel(val, mcde->regs + MCDE_TVBL1A);
1037 writel(val, mcde->regs + MCDE_TVBL2A);
1043 writel(val, mcde->regs + MCDE_TVDVOA);
1046 writel((hbp - 1), mcde->regs + MCDE_TVTIM1A);
1051 writel(val, mcde->regs + MCDE_TVLBALWA);
1054 writel(0, mcde->regs + MCDE_TVISLA);
1055 writel(0, mcde->regs + MCDE_TVBLUA);
1067 writel(val, mcde->regs + MCDE_LCDTIM1A);
1070 static void mcde_setup_dsi(struct mcde *mcde, const struct drm_display_mode *mode,
1083 dev_info(mcde->dev, "output in %s mode, format %dbpp\n",
1084 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?
1086 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));
1088 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;
1089 dev_info(mcde->dev, "Overlay CPP: %d bytes, DSI formatter CPP %d bytes\n",
1106 writel(val, mcde->regs + MCDE_CONF0);
1120 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1128 dev_dbg(mcde->dev, "FIFO watermark after flooring: %d bytes\n",
1130 dev_dbg(mcde->dev, "Packet divisor: %d bytes\n", pkt_div);
1135 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))
1138 dev_dbg(mcde->dev, "DSI packet size: %d * %d bytes per line\n",
1140 dev_dbg(mcde->dev, "Overlay frame size: %u bytes\n",
1144 dev_dbg(mcde->dev, "Formatter frame size: %u bytes\n", formatter_frame);
1158 struct mcde *mcde = to_mcde(drm);
1170 ret = regulator_enable(mcde->epod);
1181 mcde_display_disable_irqs(mcde);
1182 writel(0, mcde->regs + MCDE_IMSCERR);
1183 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
1185 if (mcde->dpi_output)
1186 mcde_setup_dpi(mcde, mode, &fifo_wtrmrk);
1188 mcde_setup_dsi(mcde, mode, cpp, &fifo_wtrmrk,
1191 mcde->stride = mode->hdisplay * cpp;
1193 mcde->stride);
1196 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);
1205 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);
1212 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,
1219 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);
1221 if (mcde->dpi_output) {
1225 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DPI_FORMATTER_0,
1229 lcd_freq = clk_round_rate(mcde->fifoa_clk, mode->clock * 1000);
1230 ret = clk_set_rate(mcde->fifoa_clk, lcd_freq);
1232 dev_err(mcde->dev, "failed to set LCD clock rate %lu Hz\n",
1234 ret = clk_prepare_enable(mcde->fifoa_clk);
1236 dev_err(mcde->dev, "failed to enable FIFO A DPI clock\n");
1239 dev_info(mcde->dev, "LCD FIFO A clk rate %lu Hz\n",
1240 clk_get_rate(mcde->fifoa_clk));
1243 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,
1250 mcde_dsi_enable(mcde->bridge);
1253 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,
1257 switch (mcde->flow_mode) {
1266 writel(val, mcde->regs + MCDE_VSCRC0);
1268 val = readl(mcde->regs + MCDE_CRC);
1270 writel(val, mcde->regs + MCDE_CRC);
1287 if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {
1288 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1289 dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");
1293 val = readl(mcde->regs + MCDE_CR);
1295 writel(val, mcde->regs + MCDE_CR);
1304 struct mcde *mcde = to_mcde(drm);
1311 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1313 if (mcde->dpi_output) {
1314 clk_disable_unprepare(mcde->fifoa_clk);
1317 mcde_dsi_disable(mcde->bridge);
1329 ret = regulator_disable(mcde->epod);
1338 static void mcde_start_flow(struct mcde *mcde)
1341 if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)
1342 mcde_dsi_te_request(mcde->mdsi);
1345 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1354 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
1357 mcde->regs + MCDE_CHNL0SYNCHSW);
1366 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1369 dev_dbg(mcde->dev, "started MCDE FIFO flow\n");
1372 static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)
1375 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);
1380 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);
1388 struct mcde *mcde = to_mcde(drm);
1411 dev_dbg(mcde->dev, "arm vblank event\n");
1414 dev_dbg(mcde->dev, "insert fake vblank event\n");
1427 mcde_set_extsrc(mcde, drm_fb_dma_get_gem_addr(fb, pstate, 0));
1428 dev_info_once(mcde->dev, "first update of display contents\n");
1433 if (mcde->flow_active == 0)
1434 mcde_start_flow(mcde);
1441 dev_info(mcde->dev, "ignored a display update\n");
1449 struct mcde *mcde = to_mcde(drm);
1459 writel(val, mcde->regs + MCDE_IMSCPP);
1468 struct mcde *mcde = to_mcde(drm);
1471 writel(0, mcde->regs + MCDE_IMSCPP);
1473 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
1487 struct mcde *mcde = to_mcde(drm);
1508 ret = mcde_init_clock_divider(mcde);
1512 ret = drm_simple_display_pipe_init(drm, &mcde->pipe,
1516 mcde->connector);