Lines Matching refs:val
24 u32 val;
26 val = lsdc_rreg32(ldev, LSDC_CRTC0_CFG_REG);
28 val &= CFG_VALID_BITS_MASK;
31 val &= ~CFG_RESET_N;
33 val &= ~CFG_PIX_FMT_MASK;
35 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val);
39 val |= CFG_RESET_N | LSDC_PF_XRGB8888 | CFG_OUTPUT_ENABLE;
41 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val);
50 u32 val;
52 val = lsdc_rreg32(ldev, LSDC_CRTC1_CFG_REG);
54 val &= CFG_VALID_BITS_MASK;
57 val &= ~CFG_RESET_N;
59 val &= ~CFG_PIX_FMT_MASK;
61 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val);
65 val |= CFG_RESET_N | LSDC_PF_XRGB8888 | CFG_OUTPUT_ENABLE;
67 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val);
76 u32 val;
78 val = lsdc_rreg32(ldev, LSDC_CRTC0_CFG_REG);
85 if (val & CRTC_ANCHORED) {
90 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val | CFG_OUTPUT_ENABLE);
105 u32 val;
112 val = lsdc_rreg32(ldev, LSDC_CRTC1_CFG_REG);
113 if (val & CRTC_ANCHORED) {
118 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val | CFG_OUTPUT_ENABLE);
135 u32 val;
137 val = lsdc_rreg32(ldev, LSDC_CRTC0_SCAN_POS_REG);
139 *hpos = val >> 16;
140 *vpos = val & 0xffff;
146 u32 val;
148 val = lsdc_rreg32(ldev, LSDC_CRTC1_SCAN_POS_REG);
150 *hpos = val >> 16;
151 *vpos = val & 0xffff;
338 u32 val = lsdc_rreg32(ldev, LSDC_CRTC0_CFG_REG);
340 val &= ~CFG_DMA_STEP_MASK;
341 val |= dma_step << CFG_DMA_STEP_SHIFT;
343 lsdc_wreg32(ldev, LSDC_CRTC0_CFG_REG, val);
350 u32 val = lsdc_rreg32(ldev, LSDC_CRTC1_CFG_REG);
352 val &= ~CFG_DMA_STEP_MASK;
353 val |= dma_step << CFG_DMA_STEP_SHIFT;
355 lsdc_wreg32(ldev, LSDC_CRTC1_CFG_REG, val);