Lines Matching defs:kmb
69 struct kmb_drm_private *kmb;
75 kmb = to_kmb(plane->dev);
76 init_disp_cfg = kmb->init_disp_cfg[plane_id];
81 drm_dbg(&kmb->drm, "Cannot change format after initial plane configuration");
96 struct kmb_drm_private *kmb;
105 kmb = to_kmb(plane->dev);
106 init_disp_cfg = kmb->init_disp_cfg[plane_id];
127 drm_dbg(&kmb->drm, "Cannot change plane height or width after initial configuration");
146 struct kmb_drm_private *kmb;
148 kmb = to_kmb(plane->dev);
155 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL1_ENABLE;
158 kmb->plane_status[plane_id].ctrl = LCD_CTRL_VL2_ENABLE;
162 kmb->plane_status[plane_id].disable = true;
286 static void config_csc(struct kmb_drm_private *kmb, int plane_id)
289 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF11(plane_id), csc_coef_lcd[0]);
290 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF12(plane_id), csc_coef_lcd[1]);
291 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF13(plane_id), csc_coef_lcd[2]);
292 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF21(plane_id), csc_coef_lcd[3]);
293 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF22(plane_id), csc_coef_lcd[4]);
294 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF23(plane_id), csc_coef_lcd[5]);
295 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF31(plane_id), csc_coef_lcd[6]);
296 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF32(plane_id), csc_coef_lcd[7]);
297 kmb_write_lcd(kmb, LCD_LAYERn_CSC_COEFF33(plane_id), csc_coef_lcd[8]);
298 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF1(plane_id), csc_coef_lcd[9]);
299 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF2(plane_id), csc_coef_lcd[10]);
300 kmb_write_lcd(kmb, LCD_LAYERn_CSC_OFF3(plane_id), csc_coef_lcd[11]);
303 static void kmb_plane_set_alpha(struct kmb_drm_private *kmb,
338 kmb_write_lcd(kmb, LCD_LAYERn_ALPHA(plane_id), plane_alpha);
349 struct kmb_drm_private *kmb;
372 kmb = to_kmb(plane->dev);
375 spin_lock_irq(&kmb->irq_lock);
376 if (kmb->kmb_under_flow || kmb->kmb_flush_done) {
377 spin_unlock_irq(&kmb->irq_lock);
378 drm_dbg(&kmb->drm, "plane_update:underflow!!!! returning");
381 spin_unlock_irq(&kmb->irq_lock);
383 init_disp_cfg = &kmb->init_disp_cfg[plane_id];
389 drm_dbg(&kmb->drm,
396 drm_dbg(&kmb->drm, "dma_len=%d ", dma_len);
397 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN(plane_id), dma_len);
398 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LEN_SHADOW(plane_id), dma_len);
399 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_VSTRIDE(plane_id),
401 kmb_write_lcd(kmb, LCD_LAYERn_DMA_LINE_WIDTH(plane_id),
405 kmb_write_lcd(kmb, LCD_LAYERn_DMA_START_ADDR(plane_id),
411 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_VSTRIDE(plane_id),
413 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CB_LINE_WIDTH(plane_id),
420 kmb_write_lcd(kmb,
424 kmb_write_lcd(kmb,
429 kmb_write_lcd(kmb,
433 kmb_write_lcd(kmb,
443 kmb_write_lcd(kmb,
447 kmb_write_lcd(kmb,
453 kmb_write_lcd(kmb, LCD_LAYERn_WIDTH(plane_id), src_w - 1);
454 kmb_write_lcd(kmb, LCD_LAYERn_HEIGHT(plane_id), src_h - 1);
455 kmb_write_lcd(kmb, LCD_LAYERn_COL_START(plane_id), crtc_x);
456 kmb_write_lcd(kmb, LCD_LAYERn_ROW_START(plane_id), crtc_y);
464 config_csc(kmb, plane_id);
467 kmb_plane_set_alpha(kmb, plane->state, plane_id, &val);
469 kmb_write_lcd(kmb, LCD_LAYERn_CFG(plane_id), val);
472 ctrl = kmb_read_lcd(kmb, LCD_CONTROL);
499 /* LCD is connected to MIPI on kmb
504 kmb_write_lcd(kmb, LCD_CONTROL, ctrl);
510 kmb_set_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA);
520 kmb_write_lcd(kmb, LCD_OUT_FORMAT_CFG, out_format);
526 kmb_write_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id), dma_cfg);
537 drm_dbg(&kmb->drm, "dma_cfg=0x%x LCD_DMA_CFG=0x%x\n", dma_cfg,
538 kmb_read_lcd(kmb, LCD_LAYERn_DMA_CFG(plane_id)));
540 kmb_set_bitmask_lcd(kmb, LCD_INT_CLEAR, LCD_INT_EOF |
542 kmb_set_bitmask_lcd(kmb, LCD_INT_ENABLE, LCD_INT_EOF |
571 struct kmb_drm_private *kmb = to_kmb(drm);
625 kmb->plane = plane;
635 kmb_clr_bitmask_lcd(kmb, LCD_CONTROL, LCD_CTRL_PIPELINE_DMA);