Lines Matching refs:val
79 u32 addr, u32 *val)
101 intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
114 *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
129 u32 val = 0;
132 SB_CRRDDA_NP, addr, &val);
134 return val;
137 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
140 SB_CRWRDA_NP, addr, &val);
145 u32 val = 0;
148 SB_CRRDDA_NP, reg, &val);
150 return val;
153 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
156 SB_CRWRDA_NP, reg, &val);
161 u32 val = 0;
164 SB_CRRDDA_NP, addr, &val);
166 return val;
171 u32 val = 0;
174 SB_CRRDDA_NP, reg, &val);
176 return val;
180 u8 port, u32 reg, u32 val)
183 SB_CRWRDA_NP, reg, &val);
188 u32 val = 0;
191 SB_CRRDDA_NP, reg, &val);
193 return val;
196 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
199 SB_CRWRDA_NP, reg, &val);
204 u32 val = 0;
207 SB_CRRDDA_NP, reg, &val);
209 return val;
212 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
215 SB_CRWRDA_NP, reg, &val);
233 u32 val = 0;
235 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
241 drm_WARN(&i915->drm, val == 0xffffffff,
243 pipe_name(pipe), reg, val);
245 return val;
249 enum pipe pipe, int reg, u32 val)
253 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
258 u32 val = 0;
261 reg, &val);
262 return val;
265 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
268 reg, &val);