Lines Matching refs:i915
32 static void __vlv_punit_get(struct drm_i915_private *i915)
46 if (IS_VALLEYVIEW(i915)) {
47 cpu_latency_qos_update_request(&i915->sb_qos, 0);
52 static void __vlv_punit_put(struct drm_i915_private *i915)
54 if (IS_VALLEYVIEW(i915))
55 cpu_latency_qos_update_request(&i915->sb_qos,
61 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
64 __vlv_punit_get(i915);
66 mutex_lock(&i915->sb_lock);
69 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
71 mutex_unlock(&i915->sb_lock);
74 __vlv_punit_put(i915);
77 static int vlv_sideband_rw(struct drm_i915_private *i915,
81 struct intel_uncore *uncore = &i915->uncore;
85 lockdep_assert_held(&i915->sb_lock);
93 drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
117 drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
127 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
131 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
137 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
139 return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
143 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
147 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
153 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
155 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
159 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
163 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
169 u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
173 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
179 void vlv_iosf_sb_write(struct drm_i915_private *i915,
182 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
186 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
190 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
196 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
198 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
202 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
206 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
212 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
214 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
218 static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
224 if (IS_CHERRYVIEW(i915))
230 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
232 u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
235 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
241 drm_WARN(&i915->drm, val == 0xffffffff,
248 void vlv_dpio_write(struct drm_i915_private *i915,
251 u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
253 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
256 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
260 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
265 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
267 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,