Lines Matching refs:set
225 #define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
226 #define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
1107 * set to a finite value.
1162 * of registers. The first set pertains to the ring generating the
1474 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1475 * this field (only one bit may be set).
1519 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1537 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1547 * This best be set to the default value (3) or the CRT won't work. No,
1616 * This bit must be set on the 830 to prevent hangs when turning off the
1640 /* This bit must be set on 855,865. */
1661 /* This bit must always be set on 965G/965GM */
1668 /* This bit must always be set on 965G */
2291 /* VSYNC/HSYNC bits new with 965, default is to be set */
3602 * correctly map to the same formats in ICL, as long as bit 23 is set to 0
4089 #define PS_Y_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_VERT_FILTER_SELECT_MASK, (set))
4091 #define PS_Y_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_Y_HORZ_FILTER_SELECT_MASK, (set))
4093 #define PS_UV_VERT_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_VERT_FILTER_SELECT_MASK, (set))
4095 #define PS_UV_HORZ_FILTER_SELECT(set) REG_FIELD_PREP(PS_UV_HORZ_FILTER_SELECT_MASK, (set))
4209 #define GLK_PS_COEF_INDEX_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4210 _ID(id, _PS_COEF_SET0_INDEX_1A, _PS_COEF_SET0_INDEX_2A) + (set) * 8, \
4211 _ID(id, _PS_COEF_SET0_INDEX_1B, _PS_COEF_SET0_INDEX_2B) + (set) * 8)
4213 #define GLK_PS_COEF_DATA_SET(pipe, id, set) _MMIO_PIPE(pipe, \
4214 _ID(id, _PS_COEF_SET0_DATA_1A, _PS_COEF_SET0_DATA_2A) + (set) * 8, \
4215 _ID(id, _PS_COEF_SET0_DATA_1B, _PS_COEF_SET0_DATA_2B) + (set) * 8)
5478 * Platforms have up to 3 power well control register sets, each set
5483 * Each control register set consists of up to 4 registers used by different
5487 * - KVMR (HSW_PWR_WELL_CTL3) (only in the main register set)