Lines Matching refs:iir
82 i915_reg_t iir, i915_reg_t ier)
90 intel_uncore_write(uncore, iir, 0xffffffff);
91 intel_uncore_posting_read(uncore, iir);
92 intel_uncore_write(uncore, iir, 0xffffffff);
93 intel_uncore_posting_read(uncore, iir);
148 i915_reg_t iir)
150 gen3_assert_iir_is_zero(uncore, iir);
263 u32 iir, gt_iir, pm_iir;
270 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
272 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
298 if (iir & I915_DISPLAY_PORT_INTERRUPT)
302 * signalled in iir */
303 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
305 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
313 if (iir)
314 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
349 u32 master_ctl, iir;
355 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR);
357 if (master_ctl == 0 && iir == 0)
380 if (iir & I915_DISPLAY_PORT_INTERRUPT)
384 * signalled in iir */
385 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
387 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
396 if (iir)
397 intel_uncore_write(&dev_priv->uncore, VLV_IIR, iir);
436 /* disable master interrupt before clearing iir */
1002 u16 iir;
1004 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
1005 if (iir == 0)
1011 * signalled in iir */
1012 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1014 if (iir & I915_MASTER_ERROR_INTERRUPT)
1017 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
1019 if (iir & I915_USER_INTERRUPT)
1020 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1022 if (iir & I915_MASTER_ERROR_INTERRUPT)
1025 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1105 u32 iir;
1107 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1108 if (iir == 0)
1114 iir & I915_DISPLAY_PORT_INTERRUPT)
1118 * signalled in iir */
1119 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1121 if (iir & I915_MASTER_ERROR_INTERRUPT)
1124 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1126 if (iir & I915_USER_INTERRUPT)
1127 intel_engine_cs_irq(to_gt(dev_priv)->engine[RCS0], iir);
1129 if (iir & I915_MASTER_ERROR_INTERRUPT)
1135 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
1231 u32 iir;
1233 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR);
1234 if (iir == 0)
1239 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1243 * signalled in iir */
1244 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1246 if (iir & I915_MASTER_ERROR_INTERRUPT)
1249 intel_uncore_write(&dev_priv->uncore, GEN2_IIR, iir);
1251 if (iir & I915_USER_INTERRUPT)
1253 iir);
1255 if (iir & I915_BSD_USER_INTERRUPT)
1257 iir >> 25);
1259 if (iir & I915_MASTER_ERROR_INTERRUPT)
1265 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);