Lines Matching refs:i915
18 struct drm_i915_private *i915 = to_i915(dev);
20 const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
38 value = to_gt(i915)->ggtt->num_fences;
41 value = !!i915->display.overlay;
44 value = !!intel_engine_lookup_user(i915,
48 value = !!intel_engine_lookup_user(i915,
52 value = !!intel_engine_lookup_user(i915,
56 value = !!intel_engine_lookup_user(i915,
60 value = HAS_LLC(i915);
63 value = HAS_WT(i915);
66 value = INTEL_PPGTT(i915);
69 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
72 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
75 value = i915_cmd_parser_get_version(i915);
88 value = i915->params.enable_hangcheck &&
89 intel_has_gpu_reset(to_gt(i915));
90 if (value && intel_has_reset_engine(to_gt(i915)))
97 value = HAS_POOLED_EU(i915);
104 if (i915->media_gt)
105 value = intel_huc_check_status(&i915->media_gt->uc.huc);
107 value = intel_huc_check_status(&to_gt(i915)->uc.huc);
112 value = intel_pxp_get_readiness_status(i915->pxp);
124 value = i915->caps.scheduler;
159 value = intel_engines_has_context_isolation(i915);
163 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
172 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
181 value = to_gt(i915)->clock_frequency;
184 value = INTEL_INFO(i915)->has_coherent_ggtt;
187 value = i915_perf_ioctl_version(i915);
190 value = i915_perf_oa_timestamp_frequency(i915);
193 drm_dbg(&i915->drm, "Unknown parameter %d\n", param->param);