Lines Matching defs:vgpu
38 void populate_pvinfo_page(struct intel_vgpu *vgpu)
40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
42 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
53 vgpu_aperture_gmadr_base(vgpu);
54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
55 vgpu_aperture_sz(vgpu);
56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
57 vgpu_hidden_gmadr_base(vgpu);
58 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
59 vgpu_hidden_sz(vgpu);
61 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
68 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
70 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
71 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
162 * @vgpu: virtual GPU
167 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
169 set_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
174 * @vgpu: virtual GPU
180 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
182 mutex_lock(&vgpu->vgpu_lock);
184 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
186 if (atomic_read(&vgpu->submission.running_workload_num)) {
187 mutex_unlock(&vgpu->vgpu_lock);
188 intel_gvt_wait_vgpu_idle(vgpu);
189 mutex_lock(&vgpu->vgpu_lock);
192 intel_vgpu_stop_schedule(vgpu);
194 mutex_unlock(&vgpu->vgpu_lock);
199 * @vgpu: virtual GPU
206 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
208 intel_gvt_deactivate_vgpu(vgpu);
210 mutex_lock(&vgpu->vgpu_lock);
211 vgpu->d3_entered = false;
212 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
213 intel_vgpu_dmabuf_cleanup(vgpu);
214 mutex_unlock(&vgpu->vgpu_lock);
219 * @vgpu: virtual GPU
224 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
226 struct intel_gvt *gvt = vgpu->gvt;
229 drm_WARN(&i915->drm, test_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status),
234 * service if no active vgpu.
237 idr_remove(&gvt->vgpu_idr, vgpu->id);
240 mutex_lock(&vgpu->vgpu_lock);
241 intel_gvt_debugfs_remove_vgpu(vgpu);
242 intel_vgpu_clean_sched_policy(vgpu);
243 intel_vgpu_clean_submission(vgpu);
244 intel_vgpu_clean_display(vgpu);
245 intel_vgpu_clean_opregion(vgpu);
246 intel_vgpu_reset_ggtt(vgpu, true);
247 intel_vgpu_clean_gtt(vgpu);
248 intel_vgpu_detach_regions(vgpu);
249 intel_vgpu_free_resource(vgpu);
250 intel_vgpu_clean_mmio(vgpu);
251 intel_vgpu_dmabuf_cleanup(vgpu);
252 mutex_unlock(&vgpu->vgpu_lock);
268 struct intel_vgpu *vgpu;
272 vgpu = vzalloc(sizeof(*vgpu));
273 if (!vgpu)
276 vgpu->id = IDLE_VGPU_IDR;
277 vgpu->gvt = gvt;
278 mutex_init(&vgpu->vgpu_lock);
281 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
283 ret = intel_vgpu_init_sched_policy(vgpu);
287 clear_bit(INTEL_VGPU_STATUS_ACTIVE, vgpu->status);
288 return vgpu;
291 vfree(vgpu);
297 * @vgpu: virtual GPU
302 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
304 mutex_lock(&vgpu->vgpu_lock);
305 intel_vgpu_clean_sched_policy(vgpu);
306 mutex_unlock(&vgpu->vgpu_lock);
308 vfree(vgpu);
311 int intel_gvt_create_vgpu(struct intel_vgpu *vgpu,
314 struct intel_gvt *gvt = vgpu->gvt;
323 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
328 vgpu->id = ret;
329 vgpu->sched_ctl.weight = conf->weight;
330 mutex_init(&vgpu->vgpu_lock);
331 mutex_init(&vgpu->dmabuf_lock);
332 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
333 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
334 idr_init_base(&vgpu->object_idr, 1);
335 intel_vgpu_init_cfg_space(vgpu, 1);
336 vgpu->d3_entered = false;
338 ret = intel_vgpu_init_mmio(vgpu);
342 ret = intel_vgpu_alloc_resource(vgpu, conf);
346 populate_pvinfo_page(vgpu);
348 ret = intel_vgpu_init_gtt(vgpu);
352 ret = intel_vgpu_init_opregion(vgpu);
356 ret = intel_vgpu_init_display(vgpu, conf->edid);
360 ret = intel_vgpu_setup_submission(vgpu);
364 ret = intel_vgpu_init_sched_policy(vgpu);
368 intel_gvt_debugfs_add_vgpu(vgpu);
370 ret = intel_gvt_set_opregion(vgpu);
375 ret = intel_gvt_set_edid(vgpu, PORT_B);
377 ret = intel_gvt_set_edid(vgpu, PORT_D);
381 intel_gvt_update_reg_whitelist(vgpu);
386 intel_vgpu_clean_sched_policy(vgpu);
388 intel_vgpu_clean_submission(vgpu);
390 intel_vgpu_clean_display(vgpu);
392 intel_vgpu_clean_opregion(vgpu);
394 intel_vgpu_clean_gtt(vgpu);
396 intel_vgpu_free_resource(vgpu);
398 intel_vgpu_clean_mmio(vgpu);
400 idr_remove(&gvt->vgpu_idr, vgpu->id);
408 * @vgpu: virtual GPU
413 * device model reset or GT reset. The caller should hold the vgpu lock.
434 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
437 struct intel_gvt *gvt = vgpu->gvt;
442 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
443 vgpu->id, dmlr, engine_mask);
445 vgpu->resetting_eng = resetting_eng;
447 intel_vgpu_stop_schedule(vgpu);
450 * scheduler when the reset is triggered by current vgpu.
453 mutex_unlock(&vgpu->vgpu_lock);
454 intel_gvt_wait_vgpu_idle(vgpu);
455 mutex_lock(&vgpu->vgpu_lock);
458 intel_vgpu_reset_submission(vgpu, resetting_eng);
461 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
463 intel_vgpu_invalidate_ppgtt(vgpu);
466 if(!vgpu->d3_entered) {
467 intel_vgpu_invalidate_ppgtt(vgpu);
468 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
470 intel_vgpu_reset_ggtt(vgpu, true);
471 intel_vgpu_reset_resource(vgpu);
474 intel_vgpu_reset_mmio(vgpu, dmlr);
475 populate_pvinfo_page(vgpu);
478 intel_vgpu_reset_display(vgpu);
479 intel_vgpu_reset_cfg_space(vgpu);
481 vgpu->failsafe = false;
486 if(vgpu->d3_entered)
487 vgpu->d3_entered = false;
489 vgpu->pv_notified = false;
493 vgpu->resetting_eng = 0;
494 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
500 * @vgpu: virtual GPU
505 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
507 mutex_lock(&vgpu->vgpu_lock);
508 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
509 mutex_unlock(&vgpu->vgpu_lock);