Lines Matching defs:engine
101 if (workload->engine->id != RCS0)
141 int ring_id = workload->engine->id;
165 if (workload->engine->id == RCS0) {
169 } else if (workload->engine->id == BCS0)
191 workload->engine->name, workload->ctx_desc.lrca,
215 context_page_num = workload->engine->context_size;
218 if (IS_BROADWELL(gvt->gt->i915) && workload->engine->id == RCS0)
268 const struct intel_engine_cs *engine)
270 struct intel_uncore *uncore = engine->uncore;
273 reg = RING_INSTDONE(engine->mmio_base);
277 reg = RING_ACTHD(engine->mmio_base);
281 reg = RING_ACTHD_UDW(engine->mmio_base);
291 shadow_ctx_notifier_block[rq->engine->id]);
293 enum intel_engine_id ring_id = rq->engine->id;
303 NULL, rq->engine);
321 workload->vgpu, rq->engine);
330 save_ring_hw_state(workload->vgpu, rq->engine);
334 save_ring_hw_state(workload->vgpu, rq->engine);
369 if (GRAPHICS_VER(req->engine->i915) == 9 && is_inhibit_context(req->context))
382 if (req->engine->emit_init_breadcrumb) {
383 err = req->engine->emit_init_breadcrumb(req);
468 rq = i915_request_create(s->shadow[workload->engine->id]);
497 if (!test_and_set_bit(workload->engine->id, s->shadow_ctx_desc_updated))
498 shadow_context_descriptor_update(s->shadow[workload->engine->id],
505 if (workload->engine->id == RCS0 &&
652 vgpu_vreg_t(workload->vgpu, RING_START(workload->engine->mmio_base)) =
751 set_context_ppgtt_from_shadow(workload, s->shadow[workload->engine->id]);
806 workload->engine->name, workload);
836 workload->engine->name, workload->req);
848 pick_next_workload(struct intel_gvt *gvt, struct intel_engine_cs *engine)
860 gvt_dbg_sched("ring %s stop - no current vgpu\n", engine->name);
865 gvt_dbg_sched("ring %s stop - will reschedule\n", engine->name);
871 list_empty(workload_q_head(scheduler->current_vgpu, engine)))
878 if (scheduler->current_workload[engine->id]) {
879 workload = scheduler->current_workload[engine->id];
881 engine->name, workload);
891 scheduler->current_workload[engine->id] =
893 engine),
896 workload = scheduler->current_workload[engine->id];
898 gvt_dbg_sched("ring %s pick new workload %p\n", engine->name, workload);
952 gvt_dbg_sched("ring id %d workload lrca %x\n", rq->engine->id,
970 ring_base = rq->engine->mmio_base;
974 context_page_num = rq->engine->context_size;
977 if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
1051 struct intel_engine_cs *engine;
1056 for_each_engine_masked(engine, vgpu->gvt->gt, engine_mask, tmp) {
1058 &s->workload_q_head[engine->id], list) {
1062 clear_bit(engine->id, s->shadow_ctx_desc_updated);
1127 * if it is in middle of engine resetting, the pending
1152 struct intel_engine_cs *engine = arg;
1153 const bool need_force_wake = GRAPHICS_VER(engine->i915) >= 9;
1154 struct intel_gvt *gvt = engine->i915->gvt;
1161 gvt_dbg_core("workload thread for ring %s started\n", engine->name);
1166 add_wait_queue(&scheduler->waitq[engine->id], &wait);
1168 workload = pick_next_workload(gvt, engine);
1174 remove_wait_queue(&scheduler->waitq[engine->id], &wait);
1180 engine->name, workload,
1183 wakeref = intel_runtime_pm_get(engine->uncore->rpm);
1186 engine->name, workload);
1189 intel_uncore_forcewake_get(engine->uncore,
1208 engine->name, workload);
1215 complete_current_workload(gvt, engine->id);
1218 intel_uncore_forcewake_put(engine->uncore,
1221 intel_runtime_pm_put(engine->uncore->rpm, wakeref);
1245 struct intel_engine_cs *engine;
1250 for_each_engine(engine, gvt->gt, i) {
1252 &engine->context_status_notifier,
1261 struct intel_engine_cs *engine;
1269 for_each_engine(engine, gvt->gt, i) {
1272 scheduler->thread[i] = kthread_run(workload_thread, engine,
1273 "gvt:%s", engine->name);
1282 atomic_notifier_chain_register(&engine->context_status_notifier,
1321 struct intel_engine_cs *engine;
1327 for_each_engine(engine, vgpu->gvt->gt, id)
1386 struct intel_engine_cs *engine;
1397 for_each_engine(engine, vgpu->gvt->gt, i) {
1403 ce = intel_context_create(engine);
1414 if (!intel_uc_wants_guc_submission(&engine->gt->uc))
1444 for_each_engine(engine, vgpu->gvt->gt, i) {
1457 * @engine_mask: either ALL_ENGINES or target engine mask
1521 intel_context_unpin(s->shadow[workload->engine->id]);
1616 * @engine: the engine
1628 const struct intel_engine_cs *engine,
1632 struct list_head *q = workload_q_head(vgpu, engine);
1662 engine->name);
1674 gvt_dbg_el("ring %s begin a new workload\n", engine->name);
1694 workload->engine = engine;
1703 if (engine->id == RCS0) {
1742 workload, engine->name, head, tail, start, ctl);
1756 with_intel_runtime_pm(engine->gt->uncore->rpm, wakeref)
1767 ret = intel_context_pin(s->shadow[engine->id]);
1783 workload_q_head(workload->vgpu, workload->engine));
1785 wake_up(&workload->vgpu->gvt->scheduler.waitq[workload->engine->id]);