Lines Matching defs:vgpu
45 * @vgpu: a vGPU
51 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
53 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
64 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
71 if (!vgpu || !p_data)
74 gvt = vgpu->gvt;
75 mutex_lock(&vgpu->vgpu_lock);
76 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
79 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
82 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
86 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
93 mutex_unlock(&vgpu->vgpu_lock);
98 * @vgpu: a vGPU
106 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
109 struct intel_gvt *gvt = vgpu->gvt;
114 if (vgpu->failsafe) {
115 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
118 mutex_lock(&vgpu->vgpu_lock);
120 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
135 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
143 ret = intel_gvt_read_gpa(vgpu, pa, p_data, bytes);
155 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
167 mutex_unlock(&vgpu->vgpu_lock);
173 * @vgpu: a vGPU
181 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
184 struct intel_gvt *gvt = vgpu->gvt;
189 if (vgpu->failsafe) {
190 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
194 mutex_lock(&vgpu->vgpu_lock);
196 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
211 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
219 ret = intel_gvt_write_gpa(vgpu, pa, p_data, bytes);
223 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
234 mutex_unlock(&vgpu->vgpu_lock);
241 * @vgpu: a vGPU
244 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
246 struct intel_gvt *gvt = vgpu->gvt;
251 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
253 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
256 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
259 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
261 if (IS_BROXTON(vgpu->gvt->gt->i915)) {
262 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
264 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
266 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
268 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
272 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
277 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
282 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
284 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
287 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
299 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
306 * @vgpu: a vGPU
311 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
313 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
315 vgpu->mmio.vreg = vzalloc(info->mmio_size);
316 if (!vgpu->mmio.vreg)
319 intel_vgpu_reset_mmio(vgpu, true);
326 * @vgpu: a vGPU
329 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
331 vfree(vgpu->mmio.vreg);
332 vgpu->mmio.vreg = NULL;