Lines Matching defs:offset
44 * intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
69 unsigned int offset = 0;
76 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
77 if (reg_is_mmio(gvt, offset)) {
79 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
82 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
84 } else if (reg_is_gtt(gvt, offset)) {
85 offset -= gvt->device_info.gtt_start_offset;
86 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
111 unsigned int offset = 0;
120 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
125 if (reg_is_gtt(gvt, offset)) {
126 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
127 !IS_ALIGNED(offset, 8)))
132 !reg_is_gtt(gvt, offset + bytes - 1)))
135 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
142 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
147 if (drm_WARN_ON(&i915->drm, !reg_is_mmio(gvt, offset + bytes - 1)))
150 if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
151 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, bytes)))
155 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
159 intel_gvt_mmio_set_accessed(gvt, offset);
165 offset, bytes);
186 unsigned int offset = 0;
196 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
201 if (reg_is_gtt(gvt, offset)) {
202 if (drm_WARN_ON(&i915->drm, !IS_ALIGNED(offset, 4) &&
203 !IS_ALIGNED(offset, 8)))
208 !reg_is_gtt(gvt, offset + bytes - 1)))
211 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
218 if (drm_WARN_ON_ONCE(&i915->drm, !reg_is_mmio(gvt, offset))) {
223 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
227 intel_gvt_mmio_set_accessed(gvt, offset);
231 gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,