Lines Matching refs:vgpu
54 static void update_upstream_irq(struct intel_vgpu *vgpu,
166 * @vgpu: a vGPU
178 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
181 struct intel_gvt *gvt = vgpu->gvt;
185 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
186 (vgpu_vreg(vgpu, reg) ^ imr));
188 vgpu_vreg(vgpu, reg) = imr;
190 ops->check_pending_irq(vgpu);
197 * @vgpu: a vGPU
208 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
211 struct intel_gvt *gvt = vgpu->gvt;
214 u32 virtual_ier = vgpu_vreg(vgpu, reg);
216 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
226 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
227 vgpu_vreg(vgpu, reg) |= ier;
229 ops->check_pending_irq(vgpu);
236 * @vgpu: a vGPU
247 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
250 struct intel_gvt *gvt = vgpu->gvt;
256 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
257 (vgpu_vreg(vgpu, reg) ^ ier));
259 vgpu_vreg(vgpu, reg) = ier;
266 update_upstream_irq(vgpu, info);
268 ops->check_pending_irq(vgpu);
275 * @vgpu: a vGPU
286 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
289 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
290 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
294 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
295 (vgpu_vreg(vgpu, reg) ^ iir));
300 vgpu_vreg(vgpu, reg) &= ~iir;
303 update_upstream_irq(vgpu, info);
324 static void update_upstream_irq(struct intel_vgpu *vgpu,
327 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
328 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
334 u32 val = vgpu_vreg(vgpu,
336 & vgpu_vreg(vgpu,
366 vgpu_vreg(vgpu, isr) &= ~clear_bits;
367 vgpu_vreg(vgpu, isr) |= set_bits;
374 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
378 update_upstream_irq(vgpu, up_irq_info);
408 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
410 unsigned long offset = vgpu->gvt->device_info.msi_cap_offset;
414 control = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_CONTROL(offset));
415 addr = *(u32 *)(vgpu_cfg_space(vgpu) + MSI_CAP_ADDRESS(offset));
416 data = *(u16 *)(vgpu_cfg_space(vgpu) + MSI_CAP_DATA(offset));
425 trace_inject_msi(vgpu->id, addr, data);
428 * When guest is powered off, msi_trigger is set to NULL, but vgpu's
430 * poweroff. If this vgpu is still used in next vm, this vgpu's pipe
431 * may be enabled, then once this vgpu is active, it will get inject
436 if (!test_bit(INTEL_VGPU_STATUS_ATTACHED, vgpu->status))
438 if (vgpu->msi_trigger && eventfd_signal(vgpu->msi_trigger, 1) != 1)
444 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
457 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
459 trace_propagate_event(vgpu->id, irq_name[event], bit);
460 set_bit(bit, (void *)&vgpu_vreg(vgpu,
467 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
469 if (!vgpu->irq.irq_warn_once[event]) {
470 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
471 vgpu->id, event, irq_name[event]);
472 vgpu->irq.irq_warn_once[event] = true;
474 propagate_event(irq, event, vgpu);
507 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
509 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
512 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
524 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
525 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
526 update_upstream_irq(vgpu, info);
529 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
531 inject_virtual_interrupt(vgpu);
653 * @vgpu: a vGPU
661 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
664 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
665 struct intel_gvt *gvt = vgpu->gvt;
673 handler(irq, event, vgpu);
675 ops->check_pending_irq(vgpu);