Lines Matching defs:value
1099 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
1103 value |= DP_AUX_CH_CTL_DONE;
1104 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
1105 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
1108 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
1110 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
1113 value &= ~(0xf << 20);
1114 value |= (len << 20);
1115 vgpu_vreg(vgpu, reg) = value;
1117 if (value & DP_AUX_CH_CTL_INTERRUPT)
1366 return display->sbi.registers[i].value;
1370 unsigned int offset, u32 value)
1390 display->sbi.registers[i].value = value;
1681 u32 value = *(u32 *)p_data;
1682 u32 cmd = value & 0xff;
1725 vgpu->id, value, *data0);
1732 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
1733 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1739 u32 value = *(u32 *)p_data;
1743 if (value != 0 &&
1744 !intel_gvt_ggtt_validate_range(vgpu, value, I915_GTT_PAGE_SIZE)) {
1745 gvt_vgpu_err("write invalid HWSP address, reg:0x%x, value:0x%x\n",
1746 offset, value);
1760 vgpu->hws_pga[engine->id] = value;
1762 vgpu->id, value, offset);
1764 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);