Lines Matching defs:pipe
836 enum pipe pipe, unsigned int train_pattern)
843 fdi_rx_imr = FDI_RX_IMR(pipe);
844 fdi_tx_ctl = FDI_TX_CTL(pipe);
845 fdi_rx_ctl = FDI_RX_CTL(pipe);
1012 u32 pipe = DSPSURF_TO_PIPE(offset);
1013 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
1016 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1018 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
1020 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
1023 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1034 u32 pipe = SPRSURF_TO_PIPE(offset);
1035 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
1038 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1040 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
1043 set_bit(event, vgpu->irq.flip_done_event[pipe]);
1053 enum pipe pipe = REG_50080_TO_PIPE(offset);
1055 int event = SKL_FLIP_EVENT(pipe, plane);
1059 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1060 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
1062 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
1068 set_bit(event, vgpu->irq.flip_done_event[pipe]);