Lines Matching defs:display
44 #include "display/intel_display_types.h"
45 #include "display/intel_dmc_regs.h"
46 #include "display/intel_dp_aux_regs.h"
47 #include "display/intel_dpio_phy.h"
48 #include "display/intel_fbc.h"
49 #include "display/intel_fdi_regs.h"
50 #include "display/intel_pps_regs.h"
51 #include "display/intel_psr_regs.h"
52 #include "display/skl_watermark_regs.h"
53 #include "display/vlv_dsi_pll_regs.h"
445 * Only PIPE_A is enabled in current vGPU display and PIPE_A is tied to
507 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc;
538 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc;
680 u32 *old_rate = &(intel_vgpu_port(vgpu, vgpu->display.port_num)->vrefresh_k);
1164 struct intel_vgpu_display *display = &vgpu->display;
1195 port = &display->ports[port_index];
1355 struct intel_vgpu_display *display = &vgpu->display;
1356 int num = display->sbi.number;
1360 if (display->sbi.registers[i].offset == sbi_offset)
1366 return display->sbi.registers[i].value;
1372 struct intel_vgpu_display *display = &vgpu->display;
1373 int num = display->sbi.number;
1377 if (display->sbi.registers[i].offset == offset)
1386 display->sbi.number++;
1389 display->sbi.registers[i].offset = offset;
1390 display->sbi.registers[i].value = value;
2269 /* display */