Lines Matching refs:gvt
184 struct intel_gvt *gvt;
192 /* Both sched_data and sched_ctl can be seen a part of the global gvt
328 /* scheduler scope lock, protect gvt and vgpu schedule related data */
354 * use it with atomic bit ops so that no need to use gvt big lock.
373 return i915->gvt;
389 static inline void intel_gvt_request_service(struct intel_gvt *gvt,
392 set_bit(service, (void *)&gvt->service_request);
393 wake_up(&gvt->service_thread_wq);
396 void intel_gvt_free_firmware(struct intel_gvt *gvt);
397 int intel_gvt_load_firmware(struct intel_gvt *gvt);
407 #define gvt_to_ggtt(gvt) ((gvt)->gt->ggtt)
410 #define gvt_aperture_sz(gvt) gvt_to_ggtt(gvt)->mappable_end
411 #define gvt_aperture_pa_base(gvt) gvt_to_ggtt(gvt)->gmadr.start
413 #define gvt_ggtt_gm_sz(gvt) gvt_to_ggtt(gvt)->vm.total
414 #define gvt_ggtt_sz(gvt) (gvt_to_ggtt(gvt)->vm.total >> PAGE_SHIFT << 3)
415 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
417 #define gvt_aperture_gmadr_base(gvt) (0)
418 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
419 + gvt_aperture_sz(gvt) - 1)
421 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
422 + gvt_aperture_sz(gvt))
423 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
424 + gvt_hidden_sz(gvt) - 1)
426 #define gvt_fence_sz(gvt) (gvt_to_ggtt(gvt)->num_fences)
435 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
474 #define for_each_active_vgpu(gvt, vgpu, id) \
475 idr_for_each_entry((&(gvt)->vgpu_idr), (vgpu), (id)) \
498 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt);
499 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt);
501 struct intel_vgpu *intel_gvt_create_idle_vgpu(struct intel_gvt *gvt);
529 #define gvt_gmadr_is_aperture(gvt, gmadr) \
530 ((gmadr >= gvt_aperture_gmadr_base(gvt)) && \
531 (gmadr <= gvt_aperture_gmadr_end(gvt)))
533 #define gvt_gmadr_is_hidden(gvt, gmadr) \
534 ((gmadr >= gvt_hidden_gmadr_base(gvt)) && \
535 (gmadr <= gvt_hidden_gmadr_end(gvt)))
537 #define gvt_gmadr_is_valid(gvt, gmadr) \
538 (gvt_gmadr_is_aperture(gvt, gmadr) || \
539 gvt_gmadr_is_hidden(gvt, gmadr))
597 * @gvt: a GVT device
602 struct intel_gvt *gvt, unsigned int offset)
604 gvt->mmio.mmio_attribute[offset >> 2] |= F_ACCESSED;
609 * @gvt: a GVT device
616 struct intel_gvt *gvt, unsigned int offset)
618 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_ACCESS;
624 * @gvt: a GVT device
629 struct intel_gvt *gvt, unsigned int offset)
631 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_ACCESS;
636 * @gvt: a GVT device
641 struct intel_gvt *gvt, unsigned int offset)
643 return gvt->mmio.mmio_attribute[offset >> 2] & F_UNALIGN;
648 * @gvt: a GVT device
656 struct intel_gvt *gvt, unsigned int offset)
658 return gvt->mmio.mmio_attribute[offset >> 2] & F_MODE_MASK;
664 * @gvt: a GVT device
672 struct intel_gvt *gvt, unsigned int offset)
674 return gvt->mmio.mmio_attribute[offset >> 2] & F_SR_IN_CTX;
681 * @gvt: a GVT device
686 struct intel_gvt *gvt, unsigned int offset)
688 gvt->mmio.mmio_attribute[offset >> 2] |= F_SR_IN_CTX;
696 * @gvt: a GVT device
701 struct intel_gvt *gvt, unsigned int offset)
703 gvt->mmio.mmio_attribute[offset >> 2] |= F_CMD_WRITE_PATCH;
709 * @gvt: a GVT device
716 struct intel_gvt *gvt, unsigned int offset)
718 return gvt->mmio.mmio_attribute[offset >> 2] & F_CMD_WRITE_PATCH;
758 void intel_gvt_debugfs_init(struct intel_gvt *gvt);
759 void intel_gvt_debugfs_clean(struct intel_gvt *gvt);