Lines Matching refs:index
279 static u64 read_pte64(struct i915_ggtt *ggtt, unsigned long index)
281 void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
293 static void write_pte64(struct i915_ggtt *ggtt, unsigned long index, u64 pte)
295 void __iomem *addr = (gen8_pte_t __iomem *)ggtt->gsm + index;
302 unsigned long index, bool hypervisor_access, unsigned long gpa,
313 (index << info->gtt_entry_size_shift),
318 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
320 e->val64 = *((u64 *)pt + index);
327 unsigned long index, bool hypervisor_access, unsigned long gpa,
338 (index << info->gtt_entry_size_shift),
343 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
345 *((u64 *)pt + index) = e->val64;
550 struct intel_gvt_gtt_entry *entry, unsigned long index,
560 entry, index, false, 0, mm->vgpu);
565 struct intel_gvt_gtt_entry *entry, unsigned long index)
567 _ppgtt_get_root_entry(mm, entry, index, true);
571 struct intel_gvt_gtt_entry *entry, unsigned long index)
573 _ppgtt_get_root_entry(mm, entry, index, false);
577 struct intel_gvt_gtt_entry *entry, unsigned long index,
584 entry, index, false, 0, mm->vgpu);
588 struct intel_gvt_gtt_entry *entry, unsigned long index)
590 _ppgtt_set_root_entry(mm, entry, index, false);
594 struct intel_gvt_gtt_entry *entry, unsigned long index)
601 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
606 struct intel_gvt_gtt_entry *entry, unsigned long index)
612 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
617 struct intel_gvt_gtt_entry *entry, unsigned long index)
623 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
627 struct intel_gvt_gtt_entry *entry, unsigned long index)
630 unsigned long offset = index;
634 if (vgpu_gmadr_is_aperture(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
637 } else if (vgpu_gmadr_is_hidden(mm->vgpu, index << I915_GTT_PAGE_SHIFT)) {
642 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
651 struct intel_gvt_gtt_entry *e, unsigned long index,
663 ret = ops->get_entry(page_table, e, index, guest,
672 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
673 type, e->type, index, e->val64);
680 struct intel_gvt_gtt_entry *e, unsigned long index,
689 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
690 type, e->type, index, e->val64);
692 return ops->set_entry(page_table, e, index, guest,
697 #define ppgtt_get_guest_entry(spt, e, index) \
699 spt->guest_page.type, e, index, true)
701 #define ppgtt_set_guest_entry(spt, e, index) \
703 spt->guest_page.type, e, index, true)
705 #define ppgtt_get_shadow_entry(spt, e, index) \
707 spt->shadow_page.type, e, index, false)
709 #define ppgtt_set_shadow_entry(spt, e, index) \
711 spt->shadow_page.type, e, index, false)
1002 unsigned long index;
1011 for_each_present_shadow_entry(spt, &e, index) {
1149 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1160 gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1189 ppgtt_set_shadow_entry(spt, se, index);
1205 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1214 gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1216 GEM_BUG_ON(index % GTT_64K_PTE_STRIDE);
1230 ppgtt_set_shadow_entry(spt, &entry, index + i);
1236 struct intel_vgpu_ppgtt_spt *spt, unsigned long index,
1264 return split_64KB_gtt_entry(vgpu, spt, index, &se);
1270 return split_2MB_gtt_entry(vgpu, spt, index, &se);
1282 ppgtt_set_shadow_entry(spt, &se, index);
1321 struct intel_gvt_gtt_entry *se, unsigned long index)
1328 spt->shadow_page.type, se->val64, index);
1330 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1331 se->type, index, se->val64);
1366 struct intel_gvt_gtt_entry *we, unsigned long index)
1374 we->val64, index);
1376 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1377 we->type, index, we->val64);
1385 ppgtt_get_shadow_entry(spt, &m, index);
1387 ppgtt_set_shadow_entry(spt, &m, index);
1389 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, we);
1408 int index;
1417 for (index = 0; index < (I915_GTT_PAGE_SIZE >>
1418 info->gtt_entry_size_shift); index++) {
1419 ops->get_entry(oos_page->mem, &old, index, false, 0, vgpu);
1420 ops->get_entry(NULL, &new, index, true,
1424 && !test_and_clear_bit(index, spt->post_shadow_bitmap))
1429 new.val64, index);
1431 ret = ppgtt_populate_shadow_entry(vgpu, spt, index, &new);
1435 ops->set_entry(oos_page->mem, &new, index, false, 0, vgpu);
1572 struct intel_gvt_gtt_entry *we, unsigned long index)
1588 ppgtt_get_shadow_entry(spt, &old_se, index);
1591 ret = ppgtt_handle_guest_entry_add(spt, we, index);
1596 ret = ppgtt_handle_guest_entry_removal(spt, &old_se, index);
1603 !(index % GTT_64K_PTE_STRIDE)) {
1609 ppgtt_set_shadow_entry(spt, &old_se, index + i);
1616 ppgtt_set_shadow_entry(spt, &old_se, index);
1620 ppgtt_set_shadow_entry(spt, &old_se, index);
1641 unsigned long index)
1643 set_bit(index, spt->post_shadow_bitmap);
1666 unsigned long index;
1673 for_each_set_bit(index, spt->post_shadow_bitmap,
1675 ppgtt_get_guest_entry(spt, &ge, index);
1678 &ge, index);
1681 clear_bit(index, spt->post_shadow_bitmap);
1696 unsigned long index;
1699 index = (pa & (PAGE_SIZE - 1)) >> info->gtt_entry_size_shift;
1701 ppgtt_get_guest_entry(spt, &we, index);
1709 (index % GTT_64K_PTE_STRIDE)) {
1710 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1711 index);
1716 ret = ppgtt_handle_guest_write_page_table(spt, &we, index);
1720 if (!test_bit(index, spt->post_shadow_bitmap)) {
1723 ppgtt_get_shadow_entry(spt, &se, index);
1724 ret = ppgtt_handle_guest_entry_removal(spt, &se, index);
1728 ppgtt_set_shadow_entry(spt, &se, index);
1730 ppgtt_set_post_shadow(spt, index);
1739 ops->set_entry(spt->guest_page.oos_page->mem, &we, index,
1760 int index;
1765 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.shadow_pdps); index++) {
1766 ppgtt_get_shadow_root_entry(mm, &se, index);
1773 ppgtt_set_shadow_root_entry(mm, &se, index);
1776 NULL, se.type, se.val64, index);
1791 int index, ret;
1801 for (index = 0; index < ARRAY_SIZE(mm->ppgtt_mm.guest_pdps); index++) {
1802 ppgtt_get_guest_root_entry(mm, &ge, index);
1808 ge.type, ge.val64, index);
1817 ppgtt_set_shadow_root_entry(mm, &se, index);
1820 NULL, se.type, se.val64, index);
2040 struct intel_gvt_gtt_entry *e, unsigned long index, bool guest)
2051 ppgtt_get_shadow_entry(s, e, index);
2053 ppgtt_get_guest_entry(s, e, index);
2147 unsigned long index = off >> info->gtt_entry_size_shift;
2154 gma = index << I915_GTT_PAGE_SHIFT;
2162 ggtt_get_guest_entry(ggtt_mm, &e, index);
2791 u32 index;
2797 index = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
2801 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2804 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2807 index = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
2811 ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2814 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);