Lines Matching refs:gvt
37 #include "gvt.h"
76 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
94 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
96 if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
100 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
102 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
105 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
305 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
318 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
330 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
343 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
553 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
580 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
596 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
608 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
619 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
629 const struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
654 struct intel_gvt *gvt = spt->vgpu->gvt;
655 const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
683 struct intel_gvt *gvt = spt->vgpu->gvt;
684 const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
740 struct device *kdev = spt->vgpu->gvt->gt->i915->drm.dev;
819 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
825 struct device *kdev = vgpu->gvt->gt->i915->drm.dev;
833 if (reclaim_one_ppgtt_mm(vgpu->gvt))
903 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
912 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
918 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
946 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
947 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
984 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1053 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1072 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1136 const struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1152 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1208 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1239 const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1267 if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M) ||
1324 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1403 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1404 struct intel_gvt *gvt = vgpu->gvt;
1405 const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1446 struct intel_gvt *gvt = vgpu->gvt;
1457 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1465 struct intel_gvt *gvt = spt->vgpu->gvt;
1477 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1502 struct intel_gvt *gvt = spt->vgpu->gvt;
1503 struct intel_gvt_gtt *gtt = &gvt->gtt;
1576 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1693 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1694 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1756 struct intel_gvt *gvt = vgpu->gvt;
1757 struct intel_gvt_gtt *gtt = &gvt->gtt;
1786 struct intel_gvt *gvt = vgpu->gvt;
1787 struct intel_gvt_gtt *gtt = &gvt->gtt;
1863 struct intel_gvt *gvt = vgpu->gvt;
1896 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1897 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1898 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1914 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1917 vgpu->gvt->device_info.gtt_entry_size));
1958 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
1960 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2005 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2007 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
2008 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2014 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2019 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2021 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
2028 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2032 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2043 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2071 struct intel_gvt *gvt = vgpu->gvt;
2072 const struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2073 const struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2146 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2183 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2197 const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2201 if (pfn != vgpu->gvt->gtt.scratch_mfn)
2208 struct intel_gvt *gvt = vgpu->gvt;
2209 const struct intel_gvt_device_info *info = &gvt->device_info;
2211 const struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2293 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2297 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2307 ggtt_invalidate(gvt->gt);
2326 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2342 for_each_engine(engine, vgpu->gvt->gt, i) {
2355 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
2357 const struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2359 vgpu->gvt->device_info.gtt_entry_size_shift;
2362 struct device *dev = vgpu->gvt->gt->i915->drm.dev;
2419 struct device *dev = vgpu->gvt->gt->i915->drm.dev;
2537 static void clean_spt_oos(struct intel_gvt *gvt)
2539 struct intel_gvt_gtt *gtt = &gvt->gtt;
2554 static int setup_spt_oos(struct intel_gvt *gvt)
2556 struct intel_gvt_gtt *gtt = &gvt->gtt;
2587 clean_spt_oos(gvt);
2679 * @gvt: GVT device
2687 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2691 struct device *dev = gvt->gt->i915->drm.dev;
2696 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2697 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2713 gvt->gtt.scratch_page = virt_to_page(page);
2714 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2717 ret = setup_spt_oos(gvt);
2721 __free_page(gvt->gtt.scratch_page);
2725 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2726 mutex_init(&gvt->gtt.ppgtt_mm_lock);
2732 * @gvt: GVT device
2738 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2740 struct device *dev = gvt->gt->i915->drm.dev;
2741 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2746 __free_page(gvt->gtt.scratch_page);
2749 clean_spt_oos(gvt);
2767 mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2769 mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2787 struct intel_gvt *gvt = vgpu->gvt;
2788 const struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2794 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2817 ggtt_invalidate(gvt->gt);
2822 * @gvt: intel gvt device
2828 void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
2837 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
2845 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2853 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);