Lines Matching refs:vgpu

52 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
54 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
71 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
73 			intel_vgpu_port(vgpu, edid->port)->edid;
129 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
131 	vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
132 	if (!vgpu->display.i2c_edid.edid_available)
133 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
134 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
138 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
141 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
144 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
146 	pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
148 	intel_vgpu_init_i2c_edid(vgpu);
162 	vgpu->display.i2c_edid.state = I2C_GMBUS;
163 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
165 	vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
166 	vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
168 	if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
169 			!intel_vgpu_port_is_dp(vgpu, port)) {
170 		vgpu->display.i2c_edid.port = port;
171 		vgpu->display.i2c_edid.edid_available = true;
172 		vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
174 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
178 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
181 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
185 	if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
187 			vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
188 			reset_gmbus_controller(vgpu);
201 			vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
202 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
215 		/* vgpu gmbus only support EDID */
220 				"vgpu%d: unsupported gmbus slave addr(0x%x)\n"
222 					vgpu->id, slave_addr);
240 			if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
242 				intel_vgpu_init_i2c_edid(vgpu);
250 				vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
262 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
274 		vgpu_vreg(vgpu, offset) = wvalue;
279 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
282 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
288 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
293 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
300 	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
302 			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
309 			byte_data = edid_get_byte(vgpu);
313 		memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
314 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
328 			intel_vgpu_init_i2c_edid(vgpu);
335 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
341 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
344 	u32 value = vgpu_vreg(vgpu, offset);
346 	if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
347 		vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
352 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
358 		vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
365  * @vgpu: a vGPU
376 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
379 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
385 		return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
387 		return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
389 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
395  * @vgpu: a vGPU
406 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
409 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
415 		return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
417 		return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
419 		return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
421 		return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
423 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
468  * @vgpu: a vGPU
476 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
481 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
482 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
490 		vgpu_vreg(vgpu, offset) = value;
497 	msg = vgpu_vreg(vgpu, offset + 4);
508 	vgpu_vreg(vgpu, offset) =
515 			intel_vgpu_init_i2c_edid(vgpu);
522 				intel_vgpu_init_i2c_edid(vgpu);
527 				if (intel_vgpu_has_monitor_on_port(vgpu,
529 					intel_vgpu_port_is_dp(vgpu, port_idx))
546 			unsigned char val = edid_get_byte(vgpu);
557 	vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
562  * @vgpu: a vGPU
567 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
569 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;