Lines Matching defs:vgpu
42 static int get_edp_pipe(struct intel_vgpu *vgpu)
44 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
62 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
64 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
66 if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE))
69 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
74 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
76 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
82 if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE)
85 if (edp_pipe_is_enabled(vgpu) &&
86 get_edp_pipe(vgpu) == pipe)
174 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
176 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
184 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
190 vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &=
192 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
193 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
194 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
195 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
199 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
203 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
208 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
210 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
214 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
219 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
222 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
224 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
226 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
228 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
230 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
231 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
232 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
234 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
235 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
237 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
239 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
240 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
242 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
243 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
251 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
252 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE;
260 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
261 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
262 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
263 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
264 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
267 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
268 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
269 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
271 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
278 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
282 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
284 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
286 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
289 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
291 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
295 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
296 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
297 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
298 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
300 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
302 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
304 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
307 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
311 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
313 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
315 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
319 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
321 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
325 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
326 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
327 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
328 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
330 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
332 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
334 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
337 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
341 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
343 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
345 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
349 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
351 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
358 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
366 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
368 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
381 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
383 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
385 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
387 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
394 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64);
395 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
396 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
397 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
398 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
401 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
402 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
404 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
406 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
408 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
409 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
412 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
417 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
419 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
422 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
423 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
424 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
427 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
428 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
430 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
432 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
434 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
435 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
438 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
443 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
445 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
448 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
449 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
450 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
453 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
454 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
456 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
458 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
460 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
461 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
464 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
469 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
471 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
474 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
475 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
476 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
483 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
484 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
487 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
489 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
492 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
494 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
499 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
503 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE;
504 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
505 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK;
506 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
509 vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE;
512 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
514 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
526 struct intel_vgpu *vgpu;
529 vgpu = container_of(vblank_timer, struct intel_vgpu, vblank_timer);
532 intel_gvt_request_service(vgpu->gvt,
533 INTEL_GVT_REQUEST_EMULATE_VBLANK + vgpu->id);
538 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
541 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
542 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
543 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
568 vgpu->display.port_num = port_num;
576 emulate_monitor_status_change(vgpu);
583 * @vgpu: vGPU operated
591 void vgpu_update_vblank_emulation(struct intel_vgpu *vgpu, bool turnon)
593 struct intel_vgpu_vblank_timer *vblank_timer = &vgpu->vblank_timer;
595 intel_vgpu_port(vgpu, vgpu->display.port_num);
622 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
624 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
625 struct intel_vgpu_irq *irq = &vgpu->irq;
639 if (!pipe_is_enabled(vgpu, pipe))
642 intel_vgpu_trigger_virtual_event(vgpu, event);
645 if (pipe_is_enabled(vgpu, pipe)) {
646 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
647 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
651 void intel_vgpu_emulate_vblank(struct intel_vgpu *vgpu)
655 mutex_lock(&vgpu->vgpu_lock);
656 for_each_pipe(vgpu->gvt->gt->i915, pipe)
657 emulate_vblank_on_pipe(vgpu, pipe);
658 mutex_unlock(&vgpu->vgpu_lock);
663 * @vgpu: a vGPU
669 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
671 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
679 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
681 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
683 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
685 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
687 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
688 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
690 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
692 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
694 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
697 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
700 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
702 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
704 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
706 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
708 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
710 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
712 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
715 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
717 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
720 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
722 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
724 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
726 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
728 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
730 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
732 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
735 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
737 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
740 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
742 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
744 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
746 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
753 * @vgpu: a vGPU
758 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
760 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
766 clean_virtual_dp_monitor(vgpu, PORT_D);
768 clean_virtual_dp_monitor(vgpu, PORT_B);
770 vgpu_update_vblank_emulation(vgpu, false);
775 * @vgpu: a vGPU
784 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
786 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
788 intel_vgpu_init_i2c_edid(vgpu);
794 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
797 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
803 * @vgpu: a vGPU
808 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
810 emulate_monitor_status_change(vgpu);