Lines Matching defs:state
197 /* Some common HW state calculation code */
203 uint8_t *regs = priv->state.regs;
234 struct ch7006_state *state = &priv->state;
242 setbitf(state, CH7006_SUBC_INC0, 28, subc_inc);
243 setbitf(state, CH7006_SUBC_INC1, 24, subc_inc);
244 setbitf(state, CH7006_SUBC_INC2, 20, subc_inc);
245 setbitf(state, CH7006_SUBC_INC3, 16, subc_inc);
246 setbitf(state, CH7006_SUBC_INC4, 12, subc_inc);
247 setbitf(state, CH7006_SUBC_INC5, 8, subc_inc);
248 setbitf(state, CH7006_SUBC_INC6, 4, subc_inc);
249 setbitf(state, CH7006_SUBC_INC7, 0, subc_inc);
258 uint8_t *regs = priv->state.regs;
295 uint8_t *power = &priv->state.regs[CH7006_POWER];
329 struct ch7006_state *state = &priv->state;
333 uint8_t *regs = state->regs;
354 setbitf(state, CH7006_POV, HPOS_8, hpos);
355 setbitf(state, CH7006_HPOS, 0, hpos);
360 setbitf(state, CH7006_POV, VPOS_8, vpos);
361 setbitf(state, CH7006_VPOS, 0, vpos);
401 struct ch7006_state *state)
403 ch7006_load_reg(client, state, CH7006_POWER);
405 ch7006_load_reg(client, state, CH7006_DISPMODE);
406 ch7006_load_reg(client, state, CH7006_FFILTER);
407 ch7006_load_reg(client, state, CH7006_BWIDTH);
408 ch7006_load_reg(client, state, CH7006_INPUT_FORMAT);
409 ch7006_load_reg(client, state, CH7006_CLKMODE);
410 ch7006_load_reg(client, state, CH7006_START_ACTIVE);
411 ch7006_load_reg(client, state, CH7006_POV);
412 ch7006_load_reg(client, state, CH7006_BLACK_LEVEL);
413 ch7006_load_reg(client, state, CH7006_HPOS);
414 ch7006_load_reg(client, state, CH7006_VPOS);
415 ch7006_load_reg(client, state, CH7006_INPUT_SYNC);
416 ch7006_load_reg(client, state, CH7006_DETECT);
417 ch7006_load_reg(client, state, CH7006_CONTRAST);
418 ch7006_load_reg(client, state, CH7006_PLLOV);
419 ch7006_load_reg(client, state, CH7006_PLLM);
420 ch7006_load_reg(client, state, CH7006_PLLN);
421 ch7006_load_reg(client, state, CH7006_BCLKOUT);
422 ch7006_load_reg(client, state, CH7006_SUBC_INC0);
423 ch7006_load_reg(client, state, CH7006_SUBC_INC1);
424 ch7006_load_reg(client, state, CH7006_SUBC_INC2);
425 ch7006_load_reg(client, state, CH7006_SUBC_INC3);
426 ch7006_load_reg(client, state, CH7006_SUBC_INC4);
427 ch7006_load_reg(client, state, CH7006_SUBC_INC5);
428 ch7006_load_reg(client, state, CH7006_SUBC_INC6);
429 ch7006_load_reg(client, state, CH7006_SUBC_INC7);
430 ch7006_load_reg(client, state, CH7006_PLL_CONTROL);
431 ch7006_load_reg(client, state, CH7006_CALC_SUBC_INC0);
435 struct ch7006_state *state)
437 ch7006_save_reg(client, state, CH7006_POWER);
439 ch7006_save_reg(client, state, CH7006_DISPMODE);
440 ch7006_save_reg(client, state, CH7006_FFILTER);
441 ch7006_save_reg(client, state, CH7006_BWIDTH);
442 ch7006_save_reg(client, state, CH7006_INPUT_FORMAT);
443 ch7006_save_reg(client, state, CH7006_CLKMODE);
444 ch7006_save_reg(client, state, CH7006_START_ACTIVE);
445 ch7006_save_reg(client, state, CH7006_POV);
446 ch7006_save_reg(client, state, CH7006_BLACK_LEVEL);
447 ch7006_save_reg(client, state, CH7006_HPOS);
448 ch7006_save_reg(client, state, CH7006_VPOS);
449 ch7006_save_reg(client, state, CH7006_INPUT_SYNC);
450 ch7006_save_reg(client, state, CH7006_DETECT);
451 ch7006_save_reg(client, state, CH7006_CONTRAST);
452 ch7006_save_reg(client, state, CH7006_PLLOV);
453 ch7006_save_reg(client, state, CH7006_PLLM);
454 ch7006_save_reg(client, state, CH7006_PLLN);
455 ch7006_save_reg(client, state, CH7006_BCLKOUT);
456 ch7006_save_reg(client, state, CH7006_SUBC_INC0);
457 ch7006_save_reg(client, state, CH7006_SUBC_INC1);
458 ch7006_save_reg(client, state, CH7006_SUBC_INC2);
459 ch7006_save_reg(client, state, CH7006_SUBC_INC3);
460 ch7006_save_reg(client, state, CH7006_SUBC_INC4);
461 ch7006_save_reg(client, state, CH7006_SUBC_INC5);
462 ch7006_save_reg(client, state, CH7006_SUBC_INC6);
463 ch7006_save_reg(client, state, CH7006_SUBC_INC7);
464 ch7006_save_reg(client, state, CH7006_PLL_CONTROL);
465 ch7006_save_reg(client, state, CH7006_CALC_SUBC_INC0);
467 state->regs[CH7006_FFILTER] = (state->regs[CH7006_FFILTER] & 0xf0) |
468 (state->regs[CH7006_FFILTER] & 0x0c) >> 2 |
469 (state->regs[CH7006_FFILTER] & 0x03) << 2;