Lines Matching defs:temp
285 u32 dspcntr, pipeconf, dpll, temp;
329 temp = htotal_calculate(adjusted_mode);
330 REG_WRITE(htot_reg, temp);
346 temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
347 HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
386 u32 temp;
395 temp = REG_READ(DSPBCNTR);
396 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
397 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
405 temp = REG_READ(PIPEBCONF);
406 if ((temp & PIPEACONF_ENABLE) != 0) {
407 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
412 temp = REG_READ(PCH_PIPEBCONF);
413 if ((temp & PIPEACONF_ENABLE) != 0) {
414 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
422 temp = REG_READ(DPLL_CTRL);
423 if ((temp & DPLL_PWRDN) == 0) {
424 REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
436 temp = REG_READ(DPLL_CTRL);
437 if ((temp & DPLL_PWRDN) != 0) {
438 REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
439 temp = REG_READ(DPLL_CLK_ENABLE);
440 REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
447 temp = REG_READ(PIPEBCONF);
448 if ((temp & PIPEACONF_ENABLE) == 0) {
449 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
454 temp = REG_READ(PCH_PIPEBCONF);
455 if ((temp & PIPEACONF_ENABLE) == 0) {
456 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
463 temp = REG_READ(DSPBCNTR);
464 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
465 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
502 u32 temp;
508 temp = 0x0;
510 temp = 0x99;
513 HDMI_WRITE(HDMI_VIDEO_REG, temp);
537 u32 temp;
539 temp = HDMI_READ(HDMI_HSR);
540 DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
542 if ((temp & HDMI_DETECT_HDP) != 0)