Lines Matching refs:psb
130 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
131 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
132 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
133 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
134 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
135 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
136 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
137 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
151 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
160 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
161 regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
162 regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
172 regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
175 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
176 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
177 regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
180 regs->psb.saveLVDS = PSB_RVDC32(LVDS);
181 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
182 regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
183 regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
184 regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
187 regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
188 regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
189 regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
190 regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
191 regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
192 regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
193 regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
196 regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
198 regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
200 regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
244 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
245 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
246 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
247 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
248 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
249 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
250 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
251 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
272 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
275 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
291 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
292 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
293 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
304 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
305 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
306 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
307 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
309 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
310 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
311 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
312 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
326 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
327 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
328 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
329 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
330 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
331 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
332 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
335 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
337 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
339 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);