Lines Matching refs:frs
157 u32 frs; /* PLL Freqency range for HSCK (post divider) */
316 u32 frs, best_diff, best_pll, best_prd, best_fbd;
329 frs = i - 1;
341 u32 divisor = (prd + 1) * (1 << frs);
381 priv->frs = frs;
593 u32 fbd, prd, frs;
604 frs = priv->frs;
606 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
607 clk_get_rate(priv->refclk), fbd, prd, frs);
619 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
626 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));