Lines Matching refs:tc
331 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr,
338 return regmap_read_poll_timeout(tc->regmap, addr, val,
343 static int tc_aux_wait_busy(struct tc_data *tc)
345 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000);
348 static int tc_aux_write_data(struct tc_data *tc, const void *data,
356 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count);
363 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size)
368 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count);
392 struct tc_data *tc = aux_to_tc(aux);
398 ret = tc_aux_wait_busy(tc);
409 ret = tc_aux_write_data(tc, msg->buffer, size);
419 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address);
423 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size));
427 ret = tc_aux_wait_busy(tc);
431 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus);
451 return tc_aux_read_data(tc, msg->buffer, size);
476 static u32 tc_srcctrl(struct tc_data *tc)
484 if (tc->link.scrambler_dis)
486 if (tc->link.spread)
488 if (tc->link.num_lanes == 2)
490 if (tc->link.rate != 162000)
495 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl)
499 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN);
509 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock)
528 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) {
536 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock,
580 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n",
585 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock,
587 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk,
600 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN);
611 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);
616 return tc_pllupdate(tc, PXL_PLLCTRL);
619 static int tc_pxl_pll_dis(struct tc_data *tc)
622 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP);
625 static int tc_stream_clock_calc(struct tc_data *tc)
642 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768);
645 static int tc_set_syspllparam(struct tc_data *tc)
650 rate = clk_get_rate(tc->refclk);
665 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate);
669 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam);
672 static int tc_aux_link_setup(struct tc_data *tc)
678 ret = tc_set_syspllparam(tc);
682 ret = regmap_write(tc->regmap, DP_PHY_CTRL,
690 ret = tc_pllupdate(tc, DP0_PLLCTRL);
694 ret = tc_pllupdate(tc, DP1_PLLCTRL);
698 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000);
700 dev_err(tc->dev, "Timeout waiting for PHY to become ready");
711 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1);
716 tc->aux.name = "TC358767 AUX i2c adapter";
717 tc->aux.dev = tc->dev;
718 tc->aux.transfer = tc_aux_transfer;
719 drm_dp_aux_init(&tc->aux);
723 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret);
727 static int tc_get_display_props(struct tc_data *tc)
735 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd,
740 revision = tc->link.dpcd[DP_DPCD_REV];
741 rate = drm_dp_max_link_rate(tc->link.dpcd);
742 num_lanes = drm_dp_max_lane_count(tc->link.dpcd);
745 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n");
749 tc->link.rate = rate;
752 dev_dbg(tc->dev, "Falling to 2 lanes\n");
756 tc->link.num_lanes = num_lanes;
758 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®);
761 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5;
763 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®);
767 tc->link.scrambler_dis = false;
769 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®);
772 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE;
774 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n",
776 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps",
777 tc->link.num_lanes,
778 drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
780 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n",
781 tc->link.spread ? "0.5%" : "0.0%",
782 tc->link.scrambler_dis ? "disabled" : "enabled");
783 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n",
784 tc->link.assr, tc->assr);
789 dev_err(tc->dev, "failed to read DPCD: %d\n", ret);
793 static int tc_set_common_video_mode(struct tc_data *tc,
804 dev_dbg(tc->dev, "set mode %dx%d\n",
806 dev_dbg(tc->dev, "H margin %d,%d sync %d\n",
808 dev_dbg(tc->dev, "V margin %d,%d sync %d\n",
810 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal);
819 ret = regmap_write(tc->regmap, VPCTRL0,
825 ret = regmap_write(tc->regmap, HTIM01,
831 ret = regmap_write(tc->regmap, HTIM02,
837 ret = regmap_write(tc->regmap, VTIM01,
843 ret = regmap_write(tc->regmap, VTIM02,
849 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */
854 ret = regmap_write(tc->regmap, TSTCTL,
864 static int tc_set_dpi_video_mode(struct tc_data *tc,
869 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC)
872 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC)
875 return regmap_write(tc->regmap, POCTRL, value);
878 static int tc_set_edp_video_mode(struct tc_data *tc,
902 out_bw = tc->link.num_lanes * tc->link.rate;
907 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY,
911 ret = regmap_write(tc->regmap, DP0_TOTALVAL,
917 ret = regmap_write(tc->regmap, DP0_STARTVAL,
923 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL,
938 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval);
950 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt);
954 ret = regmap_write(tc->regmap, DP0_MISC,
961 static int tc_wait_link_training(struct tc_data *tc)
966 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE,
969 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n");
973 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value);
980 static int tc_main_link_enable(struct tc_data *tc)
982 struct drm_dp_aux *aux = &tc->aux;
983 struct device *dev = tc->dev;
989 dev_dbg(tc->dev, "link enable\n");
991 ret = regmap_read(tc->regmap, DP0CTL, &value);
996 ret = regmap_write(tc->regmap, DP0CTL, 0);
1001 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc));
1005 ret = regmap_write(tc->regmap, DP1_SRCCTRL,
1006 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) |
1007 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0));
1011 ret = tc_set_syspllparam(tc);
1017 if (tc->link.num_lanes == 2)
1020 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1025 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1029 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1035 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1038 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl);
1040 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000);
1047 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8);
1056 * check is tc configured for same mode
1058 if (tc->assr != tc->link.assr) {
1060 tc->assr);
1062 tmp[0] = tc->assr;
1071 if (tmp[0] != tc->assr) {
1073 tc->assr);
1075 tc->link.scrambler_dis = true;
1080 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate);
1081 tmp[1] = tc->link.num_lanes;
1083 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1091 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00;
1108 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1114 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL,
1121 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1122 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1129 ret = regmap_write(tc->regmap, DP0CTL,
1130 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ?
1137 ret = tc_wait_link_training(tc);
1142 dev_err(tc->dev, "Link training phase 1 failed: %s\n",
1150 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL,
1156 ret = regmap_write(tc->regmap, DP0_SRCCTRL,
1157 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS |
1164 ret = tc_wait_link_training(tc);
1169 dev_err(tc->dev, "Link training phase 2 failed: %s\n",
1184 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) |
1191 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00;
1206 dev_err(tc->dev, "Lane 0 failed: %x\n", value);
1210 if (tc->link.num_lanes == 2) {
1214 dev_err(tc->dev, "Lane 1 failed: %x\n", value);
1219 dev_err(tc->dev, "Interlane align failed\n");
1236 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret);
1239 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret);
1243 static int tc_main_link_disable(struct tc_data *tc)
1247 dev_dbg(tc->dev, "link disable\n");
1249 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0);
1253 ret = regmap_write(tc->regmap, DP0CTL, 0);
1257 return regmap_update_bits(tc->regmap, DP_PHY_CTRL,
1262 static int tc_dsi_rx_enable(struct tc_data *tc)
1267 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25);
1268 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25);
1269 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25);
1270 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25);
1271 regmap_write(tc->regmap, PPI_D0S_ATMR, 0);
1272 regmap_write(tc->regmap, PPI_D1S_ATMR, 0);
1273 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE);
1274 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD);
1276 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) |
1278 regmap_write(tc->regmap, PPI_LANEENABLE, value);
1279 regmap_write(tc->regmap, DSI_LANEENABLE, value);
1287 ret = regmap_write(tc->regmap, SYSCTRL, value);
1293 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION);
1294 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START);
1299 static int tc_dpi_rx_enable(struct tc_data *tc)
1309 return regmap_write(tc->regmap, SYSCTRL, value);
1312 static int tc_dpi_stream_enable(struct tc_data *tc)
1316 dev_dbg(tc->dev, "enable video stream\n");
1319 ret = tc_set_syspllparam(tc);
1327 ret = tc_pllupdate(tc, DP0_PLLCTRL);
1331 ret = tc_pllupdate(tc, DP1_PLLCTRL);
1336 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1337 1000 * tc->mode.clock);
1341 ret = tc_set_common_video_mode(tc, &tc->mode);
1345 ret = tc_set_dpi_video_mode(tc, &tc->mode);
1349 return tc_dsi_rx_enable(tc);
1352 static int tc_dpi_stream_disable(struct tc_data *tc)
1354 dev_dbg(tc->dev, "disable video stream\n");
1356 tc_pxl_pll_dis(tc);
1361 static int tc_edp_stream_enable(struct tc_data *tc)
1366 dev_dbg(tc->dev, "enable video stream\n");
1379 if (tc->input_connector_dsi || tc_test_pattern) {
1380 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk),
1381 1000 * tc->mode.clock);
1386 ret = tc_set_common_video_mode(tc, &tc->mode);
1390 ret = tc_set_edp_video_mode(tc, &tc->mode);
1395 ret = tc_stream_clock_calc(tc);
1400 if (drm_dp_enhanced_frame_cap(tc->link.dpcd))
1402 ret = regmap_write(tc->regmap, DP0CTL, value);
1414 ret = regmap_write(tc->regmap, DP0CTL, value);
1419 if (tc->input_connector_dsi)
1420 return tc_dsi_rx_enable(tc);
1422 return tc_dpi_rx_enable(tc);
1425 static int tc_edp_stream_disable(struct tc_data *tc)
1429 dev_dbg(tc->dev, "disable video stream\n");
1431 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0);
1435 tc_pxl_pll_dis(tc);
1445 struct tc_data *tc = bridge_to_tc(bridge);
1448 ret = tc_dpi_stream_enable(tc);
1450 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1451 tc_main_link_disable(tc);
1460 struct tc_data *tc = bridge_to_tc(bridge);
1463 ret = tc_dpi_stream_disable(tc);
1465 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1472 struct tc_data *tc = bridge_to_tc(bridge);
1475 ret = tc_get_display_props(tc);
1477 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1481 ret = tc_main_link_enable(tc);
1483 dev_err(tc->dev, "main link enable error: %d\n", ret);
1487 ret = tc_edp_stream_enable(tc);
1489 dev_err(tc->dev, "main link stream start error: %d\n", ret);
1490 tc_main_link_disable(tc);
1499 struct tc_data *tc = bridge_to_tc(bridge);
1502 ret = tc_edp_stream_disable(tc);
1504 dev_err(tc->dev, "main link stream stop error: %d\n", ret);
1506 ret = tc_main_link_disable(tc);
1508 dev_err(tc->dev, "main link disable error: %d\n", ret);
1552 struct tc_data *tc = bridge_to_tc(bridge);
1561 avail = tc->link.num_lanes * tc->link.rate;
1573 struct tc_data *tc = bridge_to_tc(bridge);
1575 drm_mode_copy(&tc->mode, mode);
1581 struct tc_data *tc = bridge_to_tc(bridge);
1583 return drm_get_edid(connector, &tc->aux.ddc);
1588 struct tc_data *tc = connector_to_tc(connector);
1593 ret = tc_get_display_props(tc);
1595 dev_err(tc->dev, "failed to read display props: %d\n", ret);
1599 if (tc->panel_bridge) {
1600 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector);
1605 edid = tc_get_edid(&tc->bridge, connector);
1618 struct tc_data *tc = bridge_to_tc(bridge);
1623 ret = regmap_read(tc->regmap, GPIOI, &val);
1627 conn = val & BIT(tc->hpd_pin);
1638 struct tc_data *tc = connector_to_tc(connector);
1640 if (tc->hpd_pin >= 0)
1641 return tc_bridge_detect(&tc->bridge);
1643 if (tc->panel_bridge)
1661 struct tc_data *tc = bridge_to_tc(bridge);
1663 if (!tc->panel_bridge)
1666 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1667 &tc->bridge, flags);
1674 struct tc_data *tc = bridge_to_tc(bridge);
1678 if (tc->panel_bridge) {
1680 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge,
1681 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
1689 tc->aux.drm_dev = drm;
1690 ret = drm_dp_aux_register(&tc->aux);
1695 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs);
1696 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type);
1701 if (tc->hpd_pin >= 0) {
1702 if (tc->have_irq)
1703 tc->connector.polled = DRM_CONNECTOR_POLL_HPD;
1705 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
1709 drm_display_info_set_bus_formats(&tc->connector.display_info,
1711 tc->connector.display_info.bus_flags =
1715 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder);
1719 drm_dp_aux_unregister(&tc->aux);
2018 struct tc_data *tc = arg;
2022 r = regmap_read(tc->regmap, INTSTS_G, &val);
2032 regmap_read(tc->regmap, SYSSTAT, &stat);
2034 dev_err(tc->dev, "syserr %x\n", stat);
2037 if (tc->hpd_pin >= 0 && tc->bridge.dev) {
2044 bool h = val & INT_GPIO_H(tc->hpd_pin);
2045 bool lc = val & INT_GPIO_LC(tc->hpd_pin);
2047 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin,
2051 drm_kms_helper_hotplug_event(tc->bridge.dev);
2054 regmap_write(tc->regmap, INTSTS_G, val);
2059 static int tc_mipi_dsi_host_attach(struct tc_data *tc)
2061 struct device *dev = tc->dev;
2091 tc->dsi = dsi;
2106 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc)
2108 struct device *dev = tc->dev;
2125 tc->panel_bridge = bridge;
2126 tc->bridge.type = DRM_MODE_CONNECTOR_DPI;
2127 tc->bridge.funcs = &tc_dpi_bridge_funcs;
2135 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc)
2137 struct device *dev = tc->dev;
2153 tc->panel_bridge = panel_bridge;
2154 tc->bridge.type = DRM_MODE_CONNECTOR_eDP;
2156 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort;
2159 tc->bridge.funcs = &tc_edp_bridge_funcs;
2160 if (tc->hpd_pin >= 0)
2161 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT;
2162 tc->bridge.ops |= DRM_BRIDGE_OP_EDID;
2167 static int tc_probe_bridge_endpoint(struct tc_data *tc)
2169 struct device *dev = tc->dev;
2203 tc->input_connector_dsi = false;
2204 return tc_probe_edp_bridge_endpoint(tc);
2206 tc->input_connector_dsi = true;
2207 return tc_probe_dpi_bridge_endpoint(tc);
2209 tc->input_connector_dsi = true;
2210 return tc_probe_edp_bridge_endpoint(tc);
2221 struct tc_data *tc;
2224 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL);
2225 if (!tc)
2228 tc->dev = dev;
2230 ret = tc_probe_bridge_endpoint(tc);
2234 tc->refclk = devm_clk_get_enabled(dev, "ref");
2235 if (IS_ERR(tc->refclk))
2236 return dev_err_probe(dev, PTR_ERR(tc->refclk),
2243 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH);
2244 if (IS_ERR(tc->sd_gpio))
2245 return PTR_ERR(tc->sd_gpio);
2247 if (tc->sd_gpio) {
2248 gpiod_set_value_cansleep(tc->sd_gpio, 0);
2253 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
2254 if (IS_ERR(tc->reset_gpio))
2255 return PTR_ERR(tc->reset_gpio);
2257 if (tc->reset_gpio) {
2258 gpiod_set_value_cansleep(tc->reset_gpio, 1);
2262 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config);
2263 if (IS_ERR(tc->regmap)) {
2264 ret = PTR_ERR(tc->regmap);
2270 &tc->hpd_pin);
2272 tc->hpd_pin = -ENODEV;
2274 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) {
2282 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR);
2287 "tc358767-irq", tc);
2293 tc->have_irq = true;
2296 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev);
2298 dev_err(tc->dev, "can not read device ID: %d\n", ret);
2302 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) {
2303 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev);
2307 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */
2309 if (!tc->reset_gpio) {
2316 regmap_update_bits(tc->regmap, SYSRSTENB,
2319 regmap_update_bits(tc->regmap, SYSRSTENB,
2325 if (tc->hpd_pin >= 0) {
2326 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT;
2327 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin);
2330 regmap_write(tc->regmap, lcnt_reg,
2331 clk_get_rate(tc->refclk) * 2 / 1000);
2333 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin));
2335 if (tc->have_irq) {
2337 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc);
2341 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */
2342 ret = tc_aux_link_setup(tc);
2347 tc->bridge.of_node = dev->of_node;
2348 drm_bridge_add(&tc->bridge);
2350 i2c_set_clientdata(client, tc);
2352 if (tc->input_connector_dsi) { /* DSI input */
2353 ret = tc_mipi_dsi_host_attach(tc);
2355 drm_bridge_remove(&tc->bridge);
2365 struct tc_data *tc = i2c_get_clientdata(client);
2367 drm_bridge_remove(&tc->bridge);