Lines Matching refs:dsi
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
226 #define VPG_DEFS(name, dsi) \
227 ((void __force *)&((*dsi).vpg_defs.name))
229 #define REGISTER(name, mask, dsi) \
230 { #name, VPG_DEFS(name, dsi), mask, dsi }
236 struct dw_mipi_dsi *dsi;
265 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
266 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
275 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi)
277 return dsi->slave || dsi->master;
303 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
305 writel(val, dsi->base + reg);
308 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
310 return readl(dsi->base + reg);
316 struct dw_mipi_dsi *dsi = host_to_dsi(host);
317 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
321 if (device->lanes > dsi->plat_data->max_data_lanes) {
322 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n",
327 dsi->lanes = device->lanes;
328 dsi->channel = device->channel;
329 dsi->format = device->format;
330 dsi->mode_flags = device->mode_flags;
332 bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0);
337 dsi->panel_bridge = bridge;
339 drm_bridge_add(&dsi->bridge);
353 struct dw_mipi_dsi *dsi = host_to_dsi(host);
354 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
365 drm_bridge_remove(&dsi->bridge);
370 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
382 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16)
390 dsi_write(dsi, DSI_CMD_MODE_CFG, val);
392 val = dsi_read(dsi, DSI_VID_MODE_CFG);
397 dsi_write(dsi, DSI_VID_MODE_CFG, val);
400 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
405 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
409 dev_err(dsi->dev, "failed to get available command FIFO\n");
413 dsi_write(dsi, DSI_GEN_HDR, hdr_val);
416 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
420 dev_err(dsi->dev, "failed to write command FIFO\n");
427 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
439 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
443 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
448 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
452 dev_err(dsi->dev,
460 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word));
463 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
471 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
475 dev_err(dsi->dev, "Timeout during read operation\n");
481 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
485 dev_err(dsi->dev, "Read payload FIFO is empty\n");
489 val = dsi_read(dsi, DSI_GEN_PLD_DATA);
500 struct dw_mipi_dsi *dsi = host_to_dsi(host);
506 dev_err(dsi->dev, "failed to create packet: %d\n", ret);
510 dw_mipi_message_config(dsi, msg);
511 if (dsi->slave)
512 dw_mipi_message_config(dsi->slave, msg);
514 ret = dw_mipi_dsi_write(dsi, &packet);
517 if (dsi->slave) {
518 ret = dw_mipi_dsi_write(dsi->slave, &packet);
524 ret = dw_mipi_dsi_read(dsi, msg);
541 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
552 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
554 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
560 if (dsi->vpg_defs.vpg) {
562 val |= dsi->vpg_defs.vpg_horizontal ?
564 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0;
568 dsi_write(dsi, DSI_VID_MODE_CFG, val);
571 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
576 dsi_write(dsi, DSI_PWR_UP, RESET);
579 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
580 dw_mipi_dsi_video_mode_config(dsi);
582 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
586 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
588 dsi_write(dsi, DSI_LPCLK_CTRL, val);
590 dsi_write(dsi, DSI_PWR_UP, POWERUP);
593 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
595 dsi_write(dsi, DSI_PWR_UP, RESET);
596 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
599 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
601 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
611 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data,
624 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1;
626 dsi_write(dsi, DSI_PWR_UP, RESET);
633 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
637 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
642 switch (dsi->format) {
662 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
663 dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
664 dsi_write(dsi, DSI_DPI_CFG_POL, val);
667 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
669 dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
672 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
683 dsi_write(dsi, DSI_VID_PKT_SIZE,
684 dw_mipi_is_dual_mode(dsi) ?
689 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
696 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
702 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
703 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
707 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
713 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8;
723 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
736 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
737 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
739 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
740 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
742 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
743 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
746 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
756 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
757 dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
758 dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
759 dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
762 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
764 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
769 ret = phy_ops->get_timing(dsi->plat_data->priv_data,
770 dsi->lane_mbps, &timing);
772 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n");
782 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
785 dsi_write(dsi, DSI_PHY_TMR_CFG,
788 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
790 dsi_write(dsi, DSI_PHY_TMR_CFG,
796 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
801 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
805 * stop wait time should be the maximum between host dsi
808 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
809 N_LANES(dsi->lanes));
812 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
815 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
817 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
818 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
819 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
822 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
827 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
830 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
835 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
842 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
844 dsi_read(dsi, DSI_INT_ST0);
845 dsi_read(dsi, DSI_INT_ST1);
846 dsi_write(dsi, DSI_INT_MSK0, 0);
847 dsi_write(dsi, DSI_INT_MSK1, 0);
853 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
854 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
862 dw_mipi_dsi_set_mode(dsi, 0);
865 phy_ops->power_off(dsi->plat_data->priv_data);
867 if (dsi->slave) {
868 dw_mipi_dsi_disable(dsi->slave);
869 clk_disable_unprepare(dsi->slave->pclk);
870 pm_runtime_put(dsi->slave->dev);
872 dw_mipi_dsi_disable(dsi);
874 clk_disable_unprepare(dsi->pclk);
875 pm_runtime_put(dsi->dev);
878 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi)
881 if (dsi->master)
882 return dsi->master->lanes + dsi->lanes;
885 if (dsi->slave)
886 return dsi->lanes + dsi->slave->lanes;
888 /* single-dsi, so no other instance to consider */
889 return dsi->lanes;
892 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi,
895 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
896 void *priv_data = dsi->plat_data->priv_data;
898 u32 lanes = dw_mipi_dsi_get_lanes(dsi);
900 clk_prepare_enable(dsi->pclk);
902 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags,
903 lanes, dsi->format, &dsi->lane_mbps);
907 pm_runtime_get_sync(dsi->dev);
908 dw_mipi_dsi_init(dsi);
909 dw_mipi_dsi_dpi_config(dsi, adjusted_mode);
910 dw_mipi_dsi_packet_handler_config(dsi);
911 dw_mipi_dsi_video_mode_config(dsi);
912 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode);
913 dw_mipi_dsi_command_mode_config(dsi);
914 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode);
915 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode);
917 dw_mipi_dsi_dphy_init(dsi);
918 dw_mipi_dsi_dphy_timing_config(dsi);
919 dw_mipi_dsi_dphy_interface_config(dsi);
921 dw_mipi_dsi_clear_err(dsi);
927 dw_mipi_dsi_dphy_enable(dsi);
932 dw_mipi_dsi_set_mode(dsi, 0);
935 phy_ops->power_on(dsi->plat_data->priv_data);
941 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
943 /* Power up the dsi ctl into a command mode */
944 dw_mipi_dsi_mode_set(dsi, &dsi->mode);
945 if (dsi->slave)
946 dw_mipi_dsi_mode_set(dsi->slave, &dsi->mode);
953 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
956 drm_mode_copy(&dsi->mode, adjusted_mode);
962 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
965 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO);
966 if (dsi->slave)
967 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO);
975 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
976 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data;
981 dsi->mode_flags,
982 dw_mipi_dsi_get_lanes(dsi),
983 dsi->format);
991 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge);
1001 /* Attach the panel-bridge to the dsi bridge */
1002 return drm_bridge_attach(bridge->encoder, dsi->panel_bridge, bridge,
1023 struct dw_mipi_dsi *dsi;
1029 dsi = vpg->dsi;
1033 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG);
1040 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg);
1062 struct dw_mipi_dsi *dsi = data;
1064 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi),
1065 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi),
1066 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi),
1070 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL);
1071 if (!dsi->debugfs_vpg)
1075 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644,
1076 dsi->debugfs, &dsi->debugfs_vpg[i],
1080 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi)
1082 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL);
1083 if (IS_ERR(dsi->debugfs)) {
1084 dev_err(dsi->dev, "failed to create debugfs root\n");
1088 debugfs_create_files(dsi);
1091 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi)
1093 debugfs_remove_recursive(dsi->debugfs);
1094 kfree(dsi->debugfs_vpg);
1099 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { }
1100 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
1110 struct dw_mipi_dsi *dsi;
1113 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1114 if (!dsi)
1117 dsi->dev = dev;
1118 dsi->plat_data = plat_data;
1127 dsi->base = devm_platform_ioremap_resource(pdev, 0);
1128 if (IS_ERR(dsi->base))
1132 dsi->base = plat_data->base;
1135 dsi->pclk = devm_clk_get(dev, "pclk");
1136 if (IS_ERR(dsi->pclk)) {
1137 ret = PTR_ERR(dsi->pclk);
1157 ret = clk_prepare_enable(dsi->pclk);
1167 clk_disable_unprepare(dsi->pclk);
1170 dw_mipi_dsi_debugfs_init(dsi);
1173 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
1174 dsi->dsi_host.dev = dev;
1175 ret = mipi_dsi_host_register(&dsi->dsi_host);
1179 dw_mipi_dsi_debugfs_remove(dsi);
1183 dsi->bridge.driver_private = dsi;
1184 dsi->bridge.funcs = &dw_mipi_dsi_bridge_funcs;
1186 dsi->bridge.of_node = pdev->dev.of_node;
1189 return dsi;
1192 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1194 mipi_dsi_host_unregister(&dsi->dsi_host);
1196 pm_runtime_disable(dsi->dev);
1197 dw_mipi_dsi_debugfs_remove(dsi);
1200 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave)
1203 dsi->slave = slave;
1204 dsi->slave->master = dsi;
1207 dsi->slave->lanes = dsi->lanes;
1208 dsi->slave->channel = dsi->channel;
1209 dsi->slave->format = dsi->format;
1210 dsi->slave->mode_flags = dsi->mode_flags;
1225 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi)
1227 __dw_mipi_dsi_remove(dsi);
1234 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder)
1236 return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0);
1240 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi)
1249 MODULE_ALIAS("platform:dw-mipi-dsi");