Lines Matching refs:dsi
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
105 /* dsi lanes */
128 static int nwl_dsi_clear_error(struct nwl_dsi *dsi)
130 int ret = dsi->error;
132 dsi->error = 0;
136 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val)
140 if (dsi->error)
143 ret = regmap_write(dsi->regmap, reg, val);
145 DRM_DEV_ERROR(dsi->dev,
148 dsi->error = ret;
152 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg)
157 if (dsi->error)
160 ret = regmap_read(dsi->regmap, reg, &val);
162 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n",
164 dsi->error = ret;
188 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps)
190 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
192 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp,
193 dsi->lanes * 8ULL * NSEC_PER_SEC);
212 static int nwl_dsi_config_host(struct nwl_dsi *dsi)
215 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy;
217 if (dsi->lanes < 1 || dsi->lanes > 4)
220 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes);
221 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1);
223 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) {
224 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01);
225 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01);
227 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00);
228 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00);
233 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles);
234 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles);
235 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero);
236 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles);
238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles);
239 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles);
240 cycles = ps2bc(dsi, cfg->hs_exit);
241 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles);
242 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles);
244 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01);
245 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00);
246 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00);
247 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00);
250 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles);
251 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles);
253 return nwl_dsi_clear_error(dsi);
256 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi)
264 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay;
265 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start;
266 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end;
268 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay;
269 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start;
270 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end;
272 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch);
273 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch);
274 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len);
275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay);
276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch);
277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch);
278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len);
279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay);
280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock);
282 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format);
284 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n",
285 dsi->format);
288 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format);
290 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT);
291 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format);
296 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY,
298 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY,
301 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) &&
302 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE);
305 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE);
306 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256);
308 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ?
311 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode);
312 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL,
313 dsi->mode.hdisplay);
316 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch);
317 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch);
318 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len);
320 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0);
321 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1);
322 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0);
323 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0);
325 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay);
326 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1);
327 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch);
328 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch);
330 return nwl_dsi_clear_error(dsi);
333 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi)
340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable);
341 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7);
343 return nwl_dsi_clear_error(dsi);
349 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
350 struct device *dev = dsi->dev;
358 dsi->lanes = device->lanes;
359 dsi->format = device->format;
360 dsi->dsi_mode_flags = device->mode_flags;
365 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status)
367 struct device *dev = dsi->dev;
368 struct nwl_dsi_transfer *xfer = dsi->xfer;
382 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER);
383 err = nwl_dsi_clear_error(dsi);
444 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
455 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD);
473 err = nwl_dsi_clear_error(dsi);
480 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status)
482 struct nwl_dsi_transfer *xfer = dsi->xfer;
495 end_packet = nwl_dsi_read_packet(dsi, status);
502 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi)
504 struct nwl_dsi_transfer *xfer = dsi->xfer;
520 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
536 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val);
548 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) {
549 DRM_DEV_DEBUG_DRIVER(dsi->dev,
559 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val);
562 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1);
568 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host);
573 dsi->xfer = &xfer;
576 dsi->xfer = NULL;
600 ret = clk_prepare_enable(dsi->rx_esc_clk);
602 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n",
606 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n",
607 clk_get_rate(dsi->rx_esc_clk));
610 nwl_dsi_begin_transmission(dsi);
621 clk_disable_unprepare(dsi->rx_esc_clk);
634 struct nwl_dsi *dsi = data;
636 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS);
639 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n");
642 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n");
647 nwl_dsi_finish_transmission(dsi, irq_status);
652 static int nwl_dsi_mode_set(struct nwl_dsi *dsi)
654 struct device *dev = dsi->dev;
655 union phy_configure_opts *phy_cfg = &dsi->phy_cfg;
658 if (!dsi->lanes) {
659 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes);
663 ret = phy_init(dsi->phy);
669 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY);
675 ret = phy_configure(dsi->phy, phy_cfg);
681 ret = clk_prepare_enable(dsi->tx_esc_clk);
683 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n",
687 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n",
688 clk_get_rate(dsi->tx_esc_clk));
690 ret = nwl_dsi_config_host(dsi);
696 ret = nwl_dsi_config_dpi(dsi);
702 ret = phy_power_on(dsi->phy);
708 ret = nwl_dsi_init_interrupts(dsi);
715 phy_power_off(dsi->phy);
717 clk_disable_unprepare(dsi->tx_esc_clk);
719 phy_exit(dsi->phy);
724 static int nwl_dsi_disable(struct nwl_dsi *dsi)
726 struct device *dev = dsi->dev;
730 phy_power_off(dsi->phy);
731 phy_exit(dsi->phy);
733 /* Disabling the clock before the phy breaks enabling dsi again */
734 clk_disable_unprepare(dsi->tx_esc_clk);
743 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
746 nwl_dsi_disable(dsi);
748 ret = reset_control_assert(dsi->rst_dpi);
750 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret);
753 ret = reset_control_assert(dsi->rst_byte);
755 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret);
758 ret = reset_control_assert(dsi->rst_esc);
760 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret);
763 ret = reset_control_assert(dsi->rst_pclk);
765 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret);
769 clk_disable_unprepare(dsi->core_clk);
770 clk_disable_unprepare(dsi->lcdif_clk);
772 pm_runtime_put(dsi->dev);
775 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi,
782 if (dsi->lanes < 1 || dsi->lanes > 4)
787 * dphy and nwl dsi host
790 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes,
795 rate = clk_get_rate(dsi->tx_esc_clk);
796 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate);
807 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
808 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
810 if (mode->clock * bpp > 15000000 * dsi->lanes)
813 if (mode->clock * bpp < 80000 * dsi->lanes)
847 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
848 struct device *dev = dsi->dev;
853 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg);
857 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk);
860 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg));
862 drm_mode_copy(&dsi->mode, adjusted_mode);
868 if (clk_prepare_enable(dsi->lcdif_clk) < 0)
870 if (clk_prepare_enable(dsi->core_clk) < 0)
874 ret = reset_control_deassert(dsi->rst_pclk);
881 nwl_dsi_mode_set(dsi);
884 ret = reset_control_deassert(dsi->rst_esc);
889 ret = reset_control_deassert(dsi->rst_byte);
905 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
909 ret = reset_control_deassert(dsi->rst_dpi);
911 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret);
917 struct nwl_dsi *dsi = bridge_to_dsi(bridge);
920 panel_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0);
974 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi)
976 struct platform_device *pdev = to_platform_device(dsi->dev);
981 dsi->phy = devm_phy_get(dsi->dev, "dphy");
982 if (IS_ERR(dsi->phy)) {
983 ret = PTR_ERR(dsi->phy);
985 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret);
989 clk = devm_clk_get(dsi->dev, "lcdif");
992 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n",
996 dsi->lcdif_clk = clk;
998 clk = devm_clk_get(dsi->dev, "core");
1001 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n",
1005 dsi->core_clk = clk;
1007 clk = devm_clk_get(dsi->dev, "phy_ref");
1010 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n",
1014 dsi->phy_ref_clk = clk;
1016 clk = devm_clk_get(dsi->dev, "rx_esc");
1019 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n",
1023 dsi->rx_esc_clk = clk;
1025 clk = devm_clk_get(dsi->dev, "tx_esc");
1028 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n",
1032 dsi->tx_esc_clk = clk;
1034 dsi->mux = devm_mux_control_get(dsi->dev, NULL);
1035 if (IS_ERR(dsi->mux)) {
1036 ret = PTR_ERR(dsi->mux);
1038 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret);
1046 dsi->regmap =
1047 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config);
1048 if (IS_ERR(dsi->regmap)) {
1049 ret = PTR_ERR(dsi->regmap);
1050 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n",
1055 dsi->irq = platform_get_irq(pdev, 0);
1056 if (dsi->irq < 0) {
1057 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n",
1058 dsi->irq);
1059 return dsi->irq;
1062 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk");
1063 if (IS_ERR(dsi->rst_pclk)) {
1064 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n",
1065 PTR_ERR(dsi->rst_pclk));
1066 return PTR_ERR(dsi->rst_pclk);
1068 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte");
1069 if (IS_ERR(dsi->rst_byte)) {
1070 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n",
1071 PTR_ERR(dsi->rst_byte));
1072 return PTR_ERR(dsi->rst_byte);
1074 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc");
1075 if (IS_ERR(dsi->rst_esc)) {
1076 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n",
1077 PTR_ERR(dsi->rst_esc));
1078 return PTR_ERR(dsi->rst_esc);
1080 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi");
1081 if (IS_ERR(dsi->rst_dpi)) {
1082 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n",
1083 PTR_ERR(dsi->rst_dpi));
1084 return PTR_ERR(dsi->rst_dpi);
1089 static int nwl_dsi_select_input(struct nwl_dsi *dsi)
1095 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1100 remote = of_graph_get_remote_node(dsi->dev->of_node, 0,
1103 DRM_DEV_ERROR(dsi->dev,
1109 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n",
1111 ret = mux_control_try_select(dsi->mux, use_dcss);
1113 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret);
1119 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi)
1123 ret = mux_control_deselect(dsi->mux);
1125 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret);
1135 { .compatible = "fsl,imx8mq-nwl-dsi", },
1150 struct nwl_dsi *dsi;
1153 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1154 if (!dsi)
1157 dsi->dev = dev;
1159 ret = nwl_dsi_parse_dt(dsi);
1163 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0,
1164 dev_name(dev), dsi);
1166 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq,
1171 dsi->dsi_host.ops = &nwl_dsi_host_ops;
1172 dsi->dsi_host.dev = dev;
1173 ret = mipi_dsi_host_register(&dsi->dsi_host);
1181 dsi->quirks = (uintptr_t)attr->data;
1183 dsi->bridge.driver_private = dsi;
1184 dsi->bridge.funcs = &nwl_dsi_bridge_funcs;
1185 dsi->bridge.of_node = dev->of_node;
1186 dsi->bridge.timings = &nwl_dsi_timings;
1188 dev_set_drvdata(dev, dsi);
1191 ret = nwl_dsi_select_input(dsi);
1194 mipi_dsi_host_unregister(&dsi->dsi_host);
1198 drm_bridge_add(&dsi->bridge);
1204 struct nwl_dsi *dsi = platform_get_drvdata(pdev);
1206 nwl_dsi_deselect_input(dsi);
1207 mipi_dsi_host_unregister(&dsi->dsi_host);
1208 drm_bridge_remove(&dsi->bridge);