Lines Matching refs:icn
236 static void chipone_readb(struct chipone *icn, u8 reg, u8 *val)
240 ret = regmap_read(icn->regmap, reg, &pval);
245 static int chipone_writeb(struct chipone *icn, u8 reg, u8 val)
247 return regmap_write(icn->regmap, reg, val);
250 static void chipone_configure_pll(struct chipone *icn,
279 if (icn->refclk)
280 fin = icn->refclk_rate;
282 fin = icn->dsi->hs_rate / 4; /* in Hz */
326 dev_dbg(icn->dev,
329 min_delta, icn->refclk ? "EXT" : "DSI", fin,
337 chipone_writeb(icn, PLL_CTRL(6),
338 icn->refclk ? PLL_CTRL_6_EXTERNAL : PLL_CTRL_6_MIPI_CLK);
339 chipone_writeb(icn, PLL_REF_DIV, ref_div);
340 chipone_writeb(icn, PLL_INT(0), best_m);
346 struct chipone *icn = bridge_to_chipone(bridge);
348 struct drm_display_mode *mode = &icn->mode;
354 chipone_readb(icn, VENDOR_ID, id);
355 chipone_readb(icn, DEVICE_ID_H, id + 1);
356 chipone_readb(icn, DEVICE_ID_L, id + 2);
357 chipone_readb(icn, VERSION_ID, id + 3);
359 dev_dbg(icn->dev,
364 dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n");
372 if (icn->interface_i2c)
373 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C);
375 chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI);
377 chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff);
379 chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff);
385 chipone_writeb(icn, VACTIVE_HACTIVE_HI,
393 chipone_writeb(icn, HFP_LI, hfp & 0xff);
394 chipone_writeb(icn, HSYNC_LI, hsync & 0xff);
395 chipone_writeb(icn, HBP_LI, hbp & 0xff);
397 chipone_writeb(icn, HFP_HSW_HBP_HI,
402 chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay);
404 chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start);
406 chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end);
409 chipone_writeb(icn, SYNC_EVENT_DLY, 0x80);
410 chipone_writeb(icn, HFP_MIN, hfp & 0xff);
413 chipone_writeb(icn, DSI_CTRL,
414 DSI_CTRL_UNKNOWN | DSI_CTRL_DSI_LANES(icn->dsi->lanes - 1));
416 chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0);
417 chipone_writeb(icn, PLL_CTRL(12), 0xff);
418 chipone_writeb(icn, MIPI_PN_SWAP, 0x00);
424 chipone_writeb(icn, BIST_POL, pol);
427 chipone_configure_pll(icn, mode);
429 chipone_writeb(icn, SYS_CTRL(0), 0x40);
437 chipone_writeb(icn, SYS_CTRL(1), sys_ctrl_1);
440 chipone_writeb(icn, MIPI_FORCE_0, 0x20);
441 chipone_writeb(icn, PLL_CTRL(1), 0x20);
442 chipone_writeb(icn, CONFIG_FINISH, 0x10);
450 struct chipone *icn = bridge_to_chipone(bridge);
453 if (icn->vdd1) {
454 ret = regulator_enable(icn->vdd1);
456 DRM_DEV_ERROR(icn->dev,
460 if (icn->vdd2) {
461 ret = regulator_enable(icn->vdd2);
463 DRM_DEV_ERROR(icn->dev,
467 if (icn->vdd3) {
468 ret = regulator_enable(icn->vdd3);
470 DRM_DEV_ERROR(icn->dev,
474 ret = clk_prepare_enable(icn->refclk);
476 DRM_DEV_ERROR(icn->dev,
479 gpiod_set_value(icn->enable_gpio, 1);
487 struct chipone *icn = bridge_to_chipone(bridge);
489 clk_disable_unprepare(icn->refclk);
491 if (icn->vdd1)
492 regulator_disable(icn->vdd1);
494 if (icn->vdd2)
495 regulator_disable(icn->vdd2);
497 if (icn->vdd3)
498 regulator_disable(icn->vdd3);
500 gpiod_set_value(icn->enable_gpio, 0);
507 struct chipone *icn = bridge_to_chipone(bridge);
509 drm_mode_copy(&icn->mode, adjusted_mode);
512 static int chipone_dsi_attach(struct chipone *icn)
514 struct mipi_dsi_device *dsi = icn->dsi;
515 struct device *dev = icn->dev;
525 icn->dsi->lanes = 4;
527 icn->dsi->lanes = dsi_lanes;
537 dev_err(icn->dev, "failed to attach dsi\n");
542 static int chipone_dsi_host_attach(struct chipone *icn)
544 struct device *dev = icn->dev;
577 icn->dsi = dsi;
579 ret = chipone_dsi_attach(icn);
588 struct chipone *icn = bridge_to_chipone(bridge);
590 return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags);
631 static int chipone_parse_dt(struct chipone *icn)
633 struct device *dev = icn->dev;
636 icn->refclk = devm_clk_get_optional(dev, "refclk");
637 if (IS_ERR(icn->refclk)) {
638 ret = PTR_ERR(icn->refclk);
641 } else if (icn->refclk) {
642 icn->refclk_rate = clk_get_rate(icn->refclk);
643 if (icn->refclk_rate < 10000000 || icn->refclk_rate > 154000000) {
645 icn->refclk_rate);
650 icn->vdd1 = devm_regulator_get_optional(dev, "vdd1");
651 if (IS_ERR(icn->vdd1)) {
652 ret = PTR_ERR(icn->vdd1);
655 icn->vdd1 = NULL;
659 icn->vdd2 = devm_regulator_get_optional(dev, "vdd2");
660 if (IS_ERR(icn->vdd2)) {
661 ret = PTR_ERR(icn->vdd2);
664 icn->vdd2 = NULL;
668 icn->vdd3 = devm_regulator_get_optional(dev, "vdd3");
669 if (IS_ERR(icn->vdd3)) {
670 ret = PTR_ERR(icn->vdd3);
673 icn->vdd3 = NULL;
677 icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
678 if (IS_ERR(icn->enable_gpio)) {
680 return PTR_ERR(icn->enable_gpio);
683 icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0);
684 if (IS_ERR(icn->panel_bridge))
685 return PTR_ERR(icn->panel_bridge);
692 struct chipone *icn;
695 icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL);
696 if (!icn)
699 icn->dev = dev;
701 ret = chipone_parse_dt(icn);
705 icn->bridge.funcs = &chipone_bridge_funcs;
706 icn->bridge.type = DRM_MODE_CONNECTOR_DPI;
707 icn->bridge.of_node = dev->of_node;
709 *icnr = icn;
717 struct chipone *icn;
720 ret = chipone_common_probe(dev, &icn);
724 icn->regmap = devm_regmap_init(dev, &chipone_dsi_regmap_bus,
726 if (IS_ERR(icn->regmap))
727 return PTR_ERR(icn->regmap);
729 icn->interface_i2c = false;
730 icn->dsi = dsi;
732 mipi_dsi_set_drvdata(dsi, icn);
734 drm_bridge_add(&icn->bridge);
736 ret = chipone_dsi_attach(icn);
738 drm_bridge_remove(&icn->bridge);
746 struct chipone *icn;
749 ret = chipone_common_probe(dev, &icn);
753 icn->regmap = devm_regmap_init_i2c(client, &chipone_regmap_config);
754 if (IS_ERR(icn->regmap))
755 return PTR_ERR(icn->regmap);
757 icn->interface_i2c = true;
758 icn->client = client;
759 dev_set_drvdata(dev, icn);
760 i2c_set_clientdata(client, icn);
762 drm_bridge_add(&icn->bridge);
764 return chipone_dsi_host_attach(icn);
769 struct chipone *icn = mipi_dsi_get_drvdata(dsi);
772 drm_bridge_remove(&icn->bridge);