Lines Matching refs:param
575 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
764 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
770 if (finetuneDQI_L(ast, param) == false)
820 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
833 param->reg_MADJ = 0x00034C4C;
834 param->reg_SADJ = 0x00001800;
835 param->reg_DRV = 0x000000F0;
836 param->reg_PERIOD = param->dram_freq;
837 param->rodt = 0;
839 switch (param->dram_freq) {
842 param->wodt = 0;
843 param->reg_AC1 = 0x22202725;
844 param->reg_AC2 = 0xAA007613 | trap_AC2;
845 param->reg_DQSIC = 0x000000BA;
846 param->reg_MRS = 0x04001400 | trap_MRS;
847 param->reg_EMRS = 0x00000000;
848 param->reg_IOZ = 0x00000023;
849 param->reg_DQIDLY = 0x00000074;
850 param->reg_FREQ = 0x00004DC0;
851 param->madj_max = 96;
852 param->dll2_finetune_step = 3;
853 switch (param->dram_chipid) {
857 param->reg_AC2 = 0xAA007613 | trap_AC2;
860 param->reg_AC2 = 0xAA00761C | trap_AC2;
863 param->reg_AC2 = 0xAA007636 | trap_AC2;
870 param->wodt = 1;
871 param->reg_AC1 = 0x33302825;
872 param->reg_AC2 = 0xCC009617 | trap_AC2;
873 param->reg_DQSIC = 0x000000E2;
874 param->reg_MRS = 0x04001600 | trap_MRS;
875 param->reg_EMRS = 0x00000000;
876 param->reg_IOZ = 0x00000034;
877 param->reg_DRV = 0x000000FA;
878 param->reg_DQIDLY = 0x00000089;
879 param->reg_FREQ = 0x00005040;
880 param->madj_max = 96;
881 param->dll2_finetune_step = 4;
883 switch (param->dram_chipid) {
887 param->reg_AC2 = 0xCC009617 | trap_AC2;
890 param->reg_AC2 = 0xCC009622 | trap_AC2;
893 param->reg_AC2 = 0xCC00963F | trap_AC2;
900 param->wodt = 1;
901 param->reg_AC1 = 0x33302825;
902 param->reg_AC2 = 0xCC009617 | trap_AC2;
903 param->reg_DQSIC = 0x000000E2;
904 param->reg_MRS = 0x04001600 | trap_MRS;
905 param->reg_EMRS = 0x00000000;
906 param->reg_IOZ = 0x00000023;
907 param->reg_DRV = 0x000000FA;
908 param->reg_DQIDLY = 0x00000089;
909 param->reg_FREQ = 0x000050C0;
910 param->madj_max = 96;
911 param->dll2_finetune_step = 4;
913 switch (param->dram_chipid) {
917 param->reg_AC2 = 0xCC009617 | trap_AC2;
920 param->reg_AC2 = 0xCC009622 | trap_AC2;
923 param->reg_AC2 = 0xCC00963F | trap_AC2;
930 param->wodt = 0;
931 param->reg_AC1 = 0x33302926;
932 param->reg_AC2 = 0xCD44961A;
933 param->reg_DQSIC = 0x000000FC;
934 param->reg_MRS = 0x00081830;
935 param->reg_EMRS = 0x00000000;
936 param->reg_IOZ = 0x00000045;
937 param->reg_DQIDLY = 0x00000097;
938 param->reg_FREQ = 0x000052C0;
939 param->madj_max = 88;
940 param->dll2_finetune_step = 4;
944 param->wodt = 1;
945 param->reg_AC1 = 0x33302926;
946 param->reg_AC2 = 0xDE44A61D;
947 param->reg_DQSIC = 0x00000117;
948 param->reg_MRS = 0x00081A30;
949 param->reg_EMRS = 0x00000000;
950 param->reg_IOZ = 0x070000BB;
951 param->reg_DQIDLY = 0x000000A0;
952 param->reg_FREQ = 0x000054C0;
953 param->madj_max = 79;
954 param->dll2_finetune_step = 4;
958 param->wodt = 1;
959 param->rodt = 1;
960 param->reg_AC1 = 0x33302926;
961 param->reg_AC2 = 0xEF44B61E;
962 param->reg_DQSIC = 0x00000125;
963 param->reg_MRS = 0x00081A30;
964 param->reg_EMRS = 0x00000040;
965 param->reg_DRV = 0x000000F5;
966 param->reg_IOZ = 0x00000023;
967 param->reg_DQIDLY = 0x00000088;
968 param->reg_FREQ = 0x000055C0;
969 param->madj_max = 76;
970 param->dll2_finetune_step = 3;
974 param->reg_MADJ = 0x00136868;
975 param->reg_SADJ = 0x00004534;
976 param->wodt = 1;
977 param->rodt = 1;
978 param->reg_AC1 = 0x33302A37;
979 param->reg_AC2 = 0xEF56B61E;
980 param->reg_DQSIC = 0x0000013F;
981 param->reg_MRS = 0x00101A50;
982 param->reg_EMRS = 0x00000040;
983 param->reg_DRV = 0x000000FA;
984 param->reg_IOZ = 0x00000023;
985 param->reg_DQIDLY = 0x00000078;
986 param->reg_FREQ = 0x000057C0;
987 param->madj_max = 136;
988 param->dll2_finetune_step = 3;
992 param->reg_MADJ = 0x00136868;
993 param->reg_SADJ = 0x00004534;
994 param->wodt = 1;
995 param->rodt = 1;
996 param->reg_AC1 = 0x32302A37;
997 param->reg_AC2 = 0xDF56B61F;
998 param->reg_DQSIC = 0x0000014D;
999 param->reg_MRS = 0x00101A50;
1000 param->reg_EMRS = 0x00000004;
1001 param->reg_DRV = 0x000000F5;
1002 param->reg_IOZ = 0x00000023;
1003 param->reg_DQIDLY = 0x00000078;
1004 param->reg_FREQ = 0x000058C0;
1005 param->madj_max = 132;
1006 param->dll2_finetune_step = 3;
1010 param->reg_MADJ = 0x00136868;
1011 param->reg_SADJ = 0x00004534;
1012 param->wodt = 1;
1013 param->rodt = 1;
1014 param->reg_AC1 = 0x32302A37;
1015 param->reg_AC2 = 0xEF56B621;
1016 param->reg_DQSIC = 0x0000015A;
1017 param->reg_MRS = 0x02101A50;
1018 param->reg_EMRS = 0x00000004;
1019 param->reg_DRV = 0x000000F5;
1020 param->reg_IOZ = 0x00000034;
1021 param->reg_DQIDLY = 0x00000078;
1022 param->reg_FREQ = 0x000059C0;
1023 param->madj_max = 128;
1024 param->dll2_finetune_step = 3;
1028 switch (param->dram_chipid) {
1030 param->dram_config = 0x130;
1034 param->dram_config = 0x131;
1037 param->dram_config = 0x132;
1040 param->dram_config = 0x133;
1044 switch (param->vram_size) {
1047 param->dram_config |= 0x00;
1050 param->dram_config |= 0x04;
1053 param->dram_config |= 0x08;
1056 param->dram_config |= 0x0c;
1062 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1072 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1073 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1075 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1078 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1080 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1081 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1082 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1085 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1096 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1097 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1110 if ((data2 & 0xff) > param->madj_max) {
1145 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1146 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1151 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1157 if (param->wodt) {
1160 if (param->rodt) {
1161 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1166 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1169 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1185 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1198 param->reg_MADJ = 0x00034C4C;
1199 param->reg_SADJ = 0x00001800;
1200 param->reg_DRV = 0x000000F0;
1201 param->reg_PERIOD = param->dram_freq;
1202 param->rodt = 0;
1204 switch (param->dram_freq) {
1207 param->wodt = 0;
1208 param->reg_AC1 = 0x11101513;
1209 param->reg_AC2 = 0x78117011;
1210 param->reg_DQSIC = 0x00000092;
1211 param->reg_MRS = 0x00000842;
1212 param->reg_EMRS = 0x00000000;
1213 param->reg_DRV = 0x000000F0;
1214 param->reg_IOZ = 0x00000034;
1215 param->reg_DQIDLY = 0x0000005A;
1216 param->reg_FREQ = 0x00004AC0;
1217 param->madj_max = 138;
1218 param->dll2_finetune_step = 3;
1222 param->wodt = 1;
1223 param->reg_AC1 = 0x22202613;
1224 param->reg_AC2 = 0xAA009016 | trap_AC2;
1225 param->reg_DQSIC = 0x000000BA;
1226 param->reg_MRS = 0x00000A02 | trap_MRS;
1227 param->reg_EMRS = 0x00000040;
1228 param->reg_DRV = 0x000000FA;
1229 param->reg_IOZ = 0x00000034;
1230 param->reg_DQIDLY = 0x00000074;
1231 param->reg_FREQ = 0x00004DC0;
1232 param->madj_max = 96;
1233 param->dll2_finetune_step = 3;
1234 switch (param->dram_chipid) {
1237 param->reg_AC2 = 0xAA009012 | trap_AC2;
1240 param->reg_AC2 = 0xAA009016 | trap_AC2;
1243 param->reg_AC2 = 0xAA009023 | trap_AC2;
1246 param->reg_AC2 = 0xAA00903B | trap_AC2;
1253 param->wodt = 1;
1254 param->rodt = 0;
1255 param->reg_AC1 = 0x33302714;
1256 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1257 param->reg_DQSIC = 0x000000E2;
1258 param->reg_MRS = 0x00000C02 | trap_MRS;
1259 param->reg_EMRS = 0x00000040;
1260 param->reg_DRV = 0x000000FA;
1261 param->reg_IOZ = 0x00000034;
1262 param->reg_DQIDLY = 0x00000089;
1263 param->reg_FREQ = 0x00005040;
1264 param->madj_max = 96;
1265 param->dll2_finetune_step = 4;
1267 switch (param->dram_chipid) {
1269 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1273 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1276 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1279 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1287 param->wodt = 1;
1288 param->rodt = 0;
1289 param->reg_AC1 = 0x33302714;
1290 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1291 param->reg_DQSIC = 0x000000E2;
1292 param->reg_MRS = 0x00000C02 | trap_MRS;
1293 param->reg_EMRS = 0x00000040;
1294 param->reg_DRV = 0x000000FA;
1295 param->reg_IOZ = 0x00000034;
1296 param->reg_DQIDLY = 0x00000089;
1297 param->reg_FREQ = 0x000050C0;
1298 param->madj_max = 96;
1299 param->dll2_finetune_step = 4;
1301 switch (param->dram_chipid) {
1303 param->reg_AC2 = 0xCC00B016 | trap_AC2;
1307 param->reg_AC2 = 0xCC00B01B | trap_AC2;
1310 param->reg_AC2 = 0xCC00B02B | trap_AC2;
1313 param->reg_AC2 = 0xCC00B03F | trap_AC2;
1320 param->wodt = 0;
1321 param->reg_AC1 = 0x33302815;
1322 param->reg_AC2 = 0xCD44B01E;
1323 param->reg_DQSIC = 0x000000FC;
1324 param->reg_MRS = 0x00000E72;
1325 param->reg_EMRS = 0x00000000;
1326 param->reg_DRV = 0x00000000;
1327 param->reg_IOZ = 0x00000034;
1328 param->reg_DQIDLY = 0x00000097;
1329 param->reg_FREQ = 0x000052C0;
1330 param->madj_max = 88;
1331 param->dll2_finetune_step = 3;
1335 param->wodt = 1;
1336 param->rodt = 1;
1337 param->reg_AC1 = 0x33302815;
1338 param->reg_AC2 = 0xDE44C022;
1339 param->reg_DQSIC = 0x00000117;
1340 param->reg_MRS = 0x00000E72;
1341 param->reg_EMRS = 0x00000040;
1342 param->reg_DRV = 0x0000000A;
1343 param->reg_IOZ = 0x00000045;
1344 param->reg_DQIDLY = 0x000000A0;
1345 param->reg_FREQ = 0x000054C0;
1346 param->madj_max = 79;
1347 param->dll2_finetune_step = 3;
1351 param->wodt = 1;
1352 param->rodt = 1;
1353 param->reg_AC1 = 0x33302815;
1354 param->reg_AC2 = 0xEF44D024;
1355 param->reg_DQSIC = 0x00000125;
1356 param->reg_MRS = 0x00000E72;
1357 param->reg_EMRS = 0x00000004;
1358 param->reg_DRV = 0x000000F9;
1359 param->reg_IOZ = 0x00000045;
1360 param->reg_DQIDLY = 0x000000A7;
1361 param->reg_FREQ = 0x000055C0;
1362 param->madj_max = 76;
1363 param->dll2_finetune_step = 3;
1367 param->wodt = 1;
1368 param->rodt = 1;
1369 param->reg_AC1 = 0x43402915;
1370 param->reg_AC2 = 0xFF44E025;
1371 param->reg_DQSIC = 0x00000132;
1372 param->reg_MRS = 0x00000E72;
1373 param->reg_EMRS = 0x00000040;
1374 param->reg_DRV = 0x0000000A;
1375 param->reg_IOZ = 0x00000045;
1376 param->reg_DQIDLY = 0x000000AD;
1377 param->reg_FREQ = 0x000056C0;
1378 param->madj_max = 76;
1379 param->dll2_finetune_step = 3;
1383 param->wodt = 1;
1384 param->rodt = 1;
1385 param->reg_AC1 = 0x43402915;
1386 param->reg_AC2 = 0xFF44E027;
1387 param->reg_DQSIC = 0x0000013F;
1388 param->reg_MRS = 0x00000E72;
1389 param->reg_EMRS = 0x00000004;
1390 param->reg_DRV = 0x000000F5;
1391 param->reg_IOZ = 0x00000045;
1392 param->reg_DQIDLY = 0x000000B3;
1393 param->reg_FREQ = 0x000057C0;
1394 param->madj_max = 76;
1395 param->dll2_finetune_step = 3;
1399 switch (param->dram_chipid) {
1401 param->dram_config = 0x100;
1405 param->dram_config = 0x121;
1408 param->dram_config = 0x122;
1411 param->dram_config = 0x123;
1415 switch (param->vram_size) {
1418 param->dram_config |= 0x00;
1421 param->dram_config |= 0x04;
1424 param->dram_config |= 0x08;
1427 param->dram_config |= 0x0c;
1432 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1440 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1441 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1443 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1446 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1448 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1449 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1450 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1453 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1464 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1465 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1479 if ((data2 & 0xff) > param->madj_max) {
1514 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1515 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1522 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1526 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1531 if (param->wodt) {
1534 if (param->rodt) {
1535 data = data | 0x3000 | ((param->reg_AC2 & 0x60000) >> 3);
1538 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1541 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1561 struct ast2300_dram_param param;
1584 param.dram_freq = 396;
1585 param.dram_type = AST_DDR3;
1588 param.dram_type = AST_DDR2;
1591 param.dram_chipid = AST_DRAM_512Mx16;
1595 param.dram_chipid = AST_DRAM_1Gx16;
1598 param.dram_chipid = AST_DRAM_2Gx16;
1601 param.dram_chipid = AST_DRAM_4Gx16;
1607 param.vram_size = AST_VIDMEM_SIZE_8M;
1611 param.vram_size = AST_VIDMEM_SIZE_16M;
1615 param.vram_size = AST_VIDMEM_SIZE_32M;
1619 param.vram_size = AST_VIDMEM_SIZE_64M;
1623 if (param.dram_type == AST_DDR3) {
1624 get_ddr3_info(ast, ¶m);
1625 ddr3_init(ast, ¶m);
1627 get_ddr2_info(ast, ¶m);
1628 ddr2_init(ast, ¶m);
1772 u32 addr, data, param;
1787 param = 0x930023E0;
1791 param = 0x93002400;
1793 ast_moutdwm(ast, 0x1E6E2020, param);