Lines Matching refs:ast
46 struct ast_device *ast = to_ast_device(dev);
52 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, 0x00);
54 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
61 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, index, 0x00, *ext_reg_info);
67 /* ast_set_index_reg-mask(ast, AST_IO_CRTC_PORT, 0xa1, 0xff, 0x3); */
70 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x8c, 0x00, 0x01);
71 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x00, 0x00);
75 if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast))
77 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0xff, reg);
80 u32 ast_mindwm(struct ast_device *ast, u32 r)
84 ast_write32(ast, 0xf004, r & 0xffff0000);
85 ast_write32(ast, 0xf000, 0x1);
88 data = ast_read32(ast, 0xf004) & 0xffff0000;
90 return ast_read32(ast, 0x10000 + (r & 0x0000ffff));
93 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v)
96 ast_write32(ast, 0xf004, r & 0xffff0000);
97 ast_write32(ast, 0xf000, 0x1);
99 data = ast_read32(ast, 0xf004) & 0xffff0000;
101 ast_write32(ast, 0x10000 + (r & 0x0000ffff), v);
132 static u32 mmctestburst2_ast2150(struct ast_device *ast, u32 datagen)
136 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
137 ast_moutdwm(ast, 0x1e6e0070, 0x00000001 | (datagen << 3));
140 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
142 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
146 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
147 ast_moutdwm(ast, 0x1e6e0070, 0x00000003 | (datagen << 3));
150 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
152 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
156 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
157 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
162 static u32 mmctestsingle2_ast2150(struct ast_device *ast, u32 datagen)
166 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
167 ast_moutdwm(ast, 0x1e6e0070, 0x00000005 | (datagen << 3));
170 data = ast_mindwm(ast, 0x1e6e0070) & 0x40;
172 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
176 data = (ast_mindwm(ast, 0x1e6e0070) & 0x80) >> 7;
177 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
182 static int cbrtest_ast2150(struct ast_device *ast)
187 if (mmctestburst2_ast2150(ast, i))
192 static int cbrscan_ast2150(struct ast_device *ast, int busw)
197 ast_moutdwm(ast, 0x1e6e007c, pattern_AST2150[patcnt]);
199 if (cbrtest_ast2150(ast))
209 static void cbrdlli_ast2150(struct ast_device *ast, int busw)
219 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
220 data = cbrscan_ast2150(ast, busw);
236 ast_moutdwm(ast, 0x1e6e0068, dlli | (dlli << 8) | (dlli << 16) | (dlli << 24));
243 struct ast_device *ast = to_ast_device(dev);
248 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
251 if (IS_AST_GEN1(ast)) {
253 ast_write32(ast, 0xf004, 0x1e6e0000);
254 ast_write32(ast, 0xf000, 0x1);
255 ast_write32(ast, 0x10100, 0xa8);
259 } while (ast_read32(ast, 0x10100) != 0xa8);
261 if (ast->chip == AST2100 || ast->chip == AST2200)
266 ast_write32(ast, 0xf004, 0x1e6e0000);
267 ast_write32(ast, 0xf000, 0x1);
268 ast_write32(ast, 0x12000, 0x1688A8A8);
271 } while (ast_read32(ast, 0x12000) != 0x01);
273 ast_write32(ast, 0x10000, 0xfc600309);
276 } while (ast_read32(ast, 0x10000) != 0x01);
283 } else if (dram_reg_info->index == 0x4 && !IS_AST_GEN1(ast)) {
285 if (ast->dram_type == AST_DRAM_1Gx16)
287 else if (ast->dram_type == AST_DRAM_1Gx32)
290 temp = ast_read32(ast, 0x12070);
293 ast_write32(ast, 0x10000 + dram_reg_info->index, data | temp);
295 ast_write32(ast, 0x10000 + dram_reg_info->index, dram_reg_info->data);
300 data = ast_read32(ast, 0x10120);
302 data = ast_read32(ast, 0x10004);
304 cbrdlli_ast2150(ast, 16); /* 16 bits */
306 cbrdlli_ast2150(ast, 32); /* 32 bits */
309 switch (AST_GEN(ast)) {
311 temp = ast_read32(ast, 0x10140);
312 ast_write32(ast, 0x10140, temp | 0x40);
316 temp = ast_read32(ast, 0x1200c);
317 ast_write32(ast, 0x1200c, temp & 0xfffffffd);
318 temp = ast_read32(ast, 0x12040);
319 ast_write32(ast, 0x12040, temp | 0x40);
328 j = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
334 struct ast_device *ast = to_ast_device(dev);
338 if (IS_AST_GEN7(ast)) {
339 if (ast->tx_chip_types & AST_TX_ASTDP_BIT)
341 } else if (ast->config_mode == ast_use_p2a) {
342 if (IS_AST_GEN6(ast))
344 else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
351 if (ast->tx_chip_types & AST_TX_SIL164_BIT)
352 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xcf, 0x80); /* Enable DVO */
409 static bool mmc_test(struct ast_device *ast, u32 datagen, u8 test_ctl)
413 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
414 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
417 data = ast_mindwm(ast, 0x1e6e0070) & 0x3000;
421 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
425 ast_moutdwm(ast, 0x1e6e0070, 0x0);
429 static u32 mmc_test2(struct ast_device *ast, u32 datagen, u8 test_ctl)
433 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
434 ast_moutdwm(ast, 0x1e6e0070, (datagen << 3) | test_ctl);
437 data = ast_mindwm(ast, 0x1e6e0070) & 0x1000;
439 ast_moutdwm(ast, 0x1e6e0070, 0x0);
443 data = ast_mindwm(ast, 0x1e6e0078);
445 ast_moutdwm(ast, 0x1e6e0070, 0x00000000);
450 static bool mmc_test_burst(struct ast_device *ast, u32 datagen)
452 return mmc_test(ast, datagen, 0xc1);
455 static u32 mmc_test_burst2(struct ast_device *ast, u32 datagen)
457 return mmc_test2(ast, datagen, 0x41);
460 static bool mmc_test_single(struct ast_device *ast, u32 datagen)
462 return mmc_test(ast, datagen, 0xc5);
465 static u32 mmc_test_single2(struct ast_device *ast, u32 datagen)
467 return mmc_test2(ast, datagen, 0x05);
470 static bool mmc_test_single_2500(struct ast_device *ast, u32 datagen)
472 return mmc_test(ast, datagen, 0x85);
475 static int cbr_test(struct ast_device *ast)
479 data = mmc_test_single2(ast, 0);
483 data = mmc_test_burst2(ast, i);
494 static int cbr_scan(struct ast_device *ast)
500 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
502 if ((data = cbr_test(ast)) != 0) {
515 static u32 cbr_test2(struct ast_device *ast)
519 data = mmc_test_burst2(ast, 0);
522 data |= mmc_test_single2(ast, 0);
529 static u32 cbr_scan2(struct ast_device *ast)
535 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
537 if ((data = cbr_test2(ast)) != 0) {
550 static bool cbr_test3(struct ast_device *ast)
552 if (!mmc_test_burst(ast, 0))
554 if (!mmc_test_single(ast, 0))
559 static bool cbr_scan3(struct ast_device *ast)
564 ast_moutdwm(ast, 0x1e6e007c, pattern[patcnt]);
566 if (cbr_test3(ast))
575 static bool finetuneDQI_L(struct ast_device *ast, struct ast2300_dram_param *param)
586 ast_moutdwm(ast, 0x1E6E0068, 0x00001400 | (dlli << 16) | (dlli << 24));
587 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE1);
588 data = cbr_scan2(ast);
645 ast_moutdwm(ast, 0x1E6E0080, data);
670 ast_moutdwm(ast, 0x1E6E0084, data);
674 static void finetuneDQSI(struct ast_device *ast)
683 reg_mcr0c = ast_mindwm(ast, 0x1E6E000C);
684 reg_mcr18 = ast_mindwm(ast, 0x1E6E0018);
686 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
701 ast_moutdwm(ast, 0x1E6E000C, 0);
702 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18 | (dqidly << 16) | (dqsip << 23));
703 ast_moutdwm(ast, 0x1E6E000C, reg_mcr0c);
705 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
706 ast_moutdwm(ast, 0x1E6E0070, 0);
707 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE0);
708 if (cbr_scan3(ast)) {
761 ast_moutdwm(ast, 0x1E6E0018, reg_mcr18);
764 static bool cbr_dll2(struct ast_device *ast, struct ast2300_dram_param *param)
769 finetuneDQSI(ast);
770 if (finetuneDQI_L(ast, param) == false)
778 ast_moutdwm(ast, 0x1E6E0068, 0x00001300 | (dlli << 16) | (dlli << 24));
779 ast_moutdwm(ast, 0x1E6E0074, CBR_SIZE2);
780 data = cbr_scan(ast);
816 ast_moutdwm(ast, 0x1E6E0068, ast_mindwm(ast, 0x1E720058) | (dlli << 16));
820 static void get_ddr3_info(struct ast_device *ast, struct ast2300_dram_param *param)
824 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
827 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
841 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
869 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
899 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
929 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
943 ast_moutdwm(ast, 0x1E6E2020, 0x0270);
957 ast_moutdwm(ast, 0x1E6E2020, 0x0290);
973 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
991 ast_moutdwm(ast, 0x1E6E2020, 0x02E1);
1009 ast_moutdwm(ast, 0x1E6E2020, 0x0160);
1062 static void ddr3_init(struct ast_device *ast, struct ast2300_dram_param *param)
1067 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1068 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1069 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1070 ast_moutdwm(ast, 0x1E6E0034, 0x00000000);
1072 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1073 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1075 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1078 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1079 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1080 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1081 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1082 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1083 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1084 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1085 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1086 ast_moutdwm(ast, 0x1E6E0018, 0x4000A170);
1087 ast_moutdwm(ast, 0x1E6E0018, 0x00002370);
1088 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1089 ast_moutdwm(ast, 0x1E6E0040, 0xFF444444);
1090 ast_moutdwm(ast, 0x1E6E0044, 0x22222222);
1091 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1092 ast_moutdwm(ast, 0x1E6E004C, 0x00000002);
1093 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1094 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1095 ast_moutdwm(ast, 0x1E6E0054, 0);
1096 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1097 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1098 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1099 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1100 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1101 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1104 data = ast_mindwm(ast, 0x1E6E001C);
1106 data = ast_mindwm(ast, 0x1E6E001C);
1109 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1113 ast_moutdwm(ast, 0x1E6E0064, data2);
1119 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1122 ast_moutdwm(ast, 0x1E6E0068, data);
1124 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1126 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1127 ast_moutdwm(ast, 0x1E6E0018, data);
1129 ast_moutdwm(ast, 0x1E6E0018, data);
1131 data = ast_mindwm(ast, 0x1E6E001C);
1134 data = ast_mindwm(ast, 0x1E6E001C);
1137 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0068) & 0xffff);
1138 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1139 ast_moutdwm(ast, 0x1E6E0018, data);
1141 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1142 ast_moutdwm(ast, 0x1E6E000C, 0x00000040);
1145 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1146 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1147 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1148 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1149 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1150 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1151 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1152 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1153 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1155 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1163 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1166 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1169 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1172 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1173 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1175 data = ast_mindwm(ast, 0x1E6E0070);
1177 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1178 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1179 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1185 static void get_ddr2_info(struct ast_device *ast, struct ast2300_dram_param *param)
1189 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1192 trap = (ast_mindwm(ast, 0x1E6E2070) >> 25) & 0x3;
1206 ast_moutdwm(ast, 0x1E6E2020, 0x0130);
1221 ast_moutdwm(ast, 0x1E6E2020, 0x0190);
1252 ast_moutdwm(ast, 0x1E6E2020, 0x03F1);
1286 ast_moutdwm(ast, 0x1E6E2020, 0x01F0);
1319 ast_moutdwm(ast, 0x1E6E2020, 0x0230);
1334 ast_moutdwm(ast, 0x1E6E2020, 0x0261);
1350 ast_moutdwm(ast, 0x1E6E2020, 0x0120);
1366 ast_moutdwm(ast, 0x1E6E2020, 0x02A1);
1382 ast_moutdwm(ast, 0x1E6E2020, 0x0140);
1432 static void ddr2_init(struct ast_device *ast, struct ast2300_dram_param *param)
1437 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1438 ast_moutdwm(ast, 0x1E6E0018, 0x00000100);
1439 ast_moutdwm(ast, 0x1E6E0024, 0x00000000);
1440 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ);
1441 ast_moutdwm(ast, 0x1E6E0068, param->reg_SADJ);
1443 ast_moutdwm(ast, 0x1E6E0064, param->reg_MADJ | 0xC0000);
1446 ast_moutdwm(ast, 0x1E6E0004, param->dram_config);
1447 ast_moutdwm(ast, 0x1E6E0008, 0x90040f);
1448 ast_moutdwm(ast, 0x1E6E0010, param->reg_AC1);
1449 ast_moutdwm(ast, 0x1E6E0014, param->reg_AC2);
1450 ast_moutdwm(ast, 0x1E6E0020, param->reg_DQSIC);
1451 ast_moutdwm(ast, 0x1E6E0080, 0x00000000);
1452 ast_moutdwm(ast, 0x1E6E0084, 0x00000000);
1453 ast_moutdwm(ast, 0x1E6E0088, param->reg_DQIDLY);
1454 ast_moutdwm(ast, 0x1E6E0018, 0x4000A130);
1455 ast_moutdwm(ast, 0x1E6E0018, 0x00002330);
1456 ast_moutdwm(ast, 0x1E6E0038, 0x00000000);
1457 ast_moutdwm(ast, 0x1E6E0040, 0xFF808000);
1458 ast_moutdwm(ast, 0x1E6E0044, 0x88848466);
1459 ast_moutdwm(ast, 0x1E6E0048, 0x44440008);
1460 ast_moutdwm(ast, 0x1E6E004C, 0x00000000);
1461 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1462 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1463 ast_moutdwm(ast, 0x1E6E0054, 0);
1464 ast_moutdwm(ast, 0x1E6E0060, param->reg_DRV);
1465 ast_moutdwm(ast, 0x1E6E006C, param->reg_IOZ);
1466 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1467 ast_moutdwm(ast, 0x1E6E0074, 0x00000000);
1468 ast_moutdwm(ast, 0x1E6E0078, 0x00000000);
1469 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1473 data = ast_mindwm(ast, 0x1E6E001C);
1475 data = ast_mindwm(ast, 0x1E6E001C);
1478 data2 = (ast_mindwm(ast, 0x1E6E0064) & 0xfff3ffff) + 4;
1482 ast_moutdwm(ast, 0x1E6E0064, data2);
1488 data = ast_mindwm(ast, 0x1E6E0068) & 0xffff00ff;
1491 ast_moutdwm(ast, 0x1E6E0068, data);
1493 ast_moutdwm(ast, 0x1E6E0064, ast_mindwm(ast, 0x1E6E0064) | 0xC0000);
1495 data = ast_mindwm(ast, 0x1E6E0018) & 0xfffff1ff;
1496 ast_moutdwm(ast, 0x1E6E0018, data);
1498 ast_moutdwm(ast, 0x1E6E0018, data);
1500 data = ast_mindwm(ast, 0x1E6E001C);
1503 data = ast_mindwm(ast, 0x1E6E001C);
1506 ast_moutdwm(ast, 0x1E720058, ast_mindwm(ast, 0x1E6E0008) & 0xffff);
1507 data = ast_mindwm(ast, 0x1E6E0018) | 0xC00;
1508 ast_moutdwm(ast, 0x1E6E0018, data);
1510 ast_moutdwm(ast, 0x1E6E0034, 0x00000001);
1511 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1514 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS | 0x100);
1515 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1516 ast_moutdwm(ast, 0x1E6E0028, 0x00000005);
1517 ast_moutdwm(ast, 0x1E6E0028, 0x00000007);
1518 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1519 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1521 ast_moutdwm(ast, 0x1E6E000C, 0x00005C08);
1522 ast_moutdwm(ast, 0x1E6E002C, param->reg_MRS);
1523 ast_moutdwm(ast, 0x1E6E0028, 0x00000001);
1524 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS | 0x380);
1525 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1526 ast_moutdwm(ast, 0x1E6E0030, param->reg_EMRS);
1527 ast_moutdwm(ast, 0x1E6E0028, 0x00000003);
1529 ast_moutdwm(ast, 0x1E6E000C, 0x7FFF5C01);
1537 ast_moutdwm(ast, 0x1E6E0034, data | 0x3);
1538 ast_moutdwm(ast, 0x1E6E0120, param->reg_FREQ);
1541 if ((cbr_dll2(ast, param) == false) && (retry++ < 10))
1546 ast_moutdwm(ast, 0x1E6E007C, 0x00000000);
1547 ast_moutdwm(ast, 0x1E6E0070, 0x221);
1549 data = ast_mindwm(ast, 0x1E6E0070);
1551 ast_moutdwm(ast, 0x1E6E0070, 0x00000000);
1552 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1553 ast_moutdwm(ast, 0x1E6E0050, 0x00000000);
1560 struct ast_device *ast = to_ast_device(dev);
1565 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1567 ast_write32(ast, 0xf004, 0x1e6e0000);
1568 ast_write32(ast, 0xf000, 0x1);
1569 ast_write32(ast, 0x12000, 0x1688a8a8);
1572 } while (ast_read32(ast, 0x12000) != 0x1);
1574 ast_write32(ast, 0x10000, 0xfc600309);
1577 } while (ast_read32(ast, 0x10000) != 0x1);
1580 temp = ast_read32(ast, 0x12008);
1582 ast_write32(ast, 0x12008, temp);
1586 temp = ast_mindwm(ast, 0x1e6e2070);
1624 get_ddr3_info(ast, ¶m);
1625 ddr3_init(ast, ¶m);
1627 get_ddr2_info(ast, ¶m);
1628 ddr2_init(ast, ¶m);
1631 temp = ast_mindwm(ast, 0x1e6e2040);
1632 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
1637 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
1641 static bool cbr_test_2500(struct ast_device *ast)
1643 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1644 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1645 if (!mmc_test_burst(ast, 0))
1647 if (!mmc_test_single_2500(ast, 0))
1652 static bool ddr_test_2500(struct ast_device *ast)
1654 ast_moutdwm(ast, 0x1E6E0074, 0x0000FFFF);
1655 ast_moutdwm(ast, 0x1E6E007C, 0xFF00FF00);
1656 if (!mmc_test_burst(ast, 0))
1658 if (!mmc_test_burst(ast, 1))
1660 if (!mmc_test_burst(ast, 2))
1662 if (!mmc_test_burst(ast, 3))
1664 if (!mmc_test_single_2500(ast, 0))
1669 static void ddr_init_common_2500(struct ast_device *ast)
1671 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1672 ast_moutdwm(ast, 0x1E6E0008, 0x2003000F);
1673 ast_moutdwm(ast, 0x1E6E0038, 0x00000FFF);
1674 ast_moutdwm(ast, 0x1E6E0040, 0x88448844);
1675 ast_moutdwm(ast, 0x1E6E0044, 0x24422288);
1676 ast_moutdwm(ast, 0x1E6E0048, 0x22222222);
1677 ast_moutdwm(ast, 0x1E6E004C, 0x22222222);
1678 ast_moutdwm(ast, 0x1E6E0050, 0x80000000);
1679 ast_moutdwm(ast, 0x1E6E0208, 0x00000000);
1680 ast_moutdwm(ast, 0x1E6E0218, 0x00000000);
1681 ast_moutdwm(ast, 0x1E6E0220, 0x00000000);
1682 ast_moutdwm(ast, 0x1E6E0228, 0x00000000);
1683 ast_moutdwm(ast, 0x1E6E0230, 0x00000000);
1684 ast_moutdwm(ast, 0x1E6E02A8, 0x00000000);
1685 ast_moutdwm(ast, 0x1E6E02B0, 0x00000000);
1686 ast_moutdwm(ast, 0x1E6E0240, 0x86000000);
1687 ast_moutdwm(ast, 0x1E6E0244, 0x00008600);
1688 ast_moutdwm(ast, 0x1E6E0248, 0x80000000);
1689 ast_moutdwm(ast, 0x1E6E024C, 0x80808080);
1692 static void ddr_phy_init_2500(struct ast_device *ast)
1697 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1700 data = ast_mindwm(ast, 0x1E6E0060) & 0x1;
1705 data = ast_mindwm(ast, 0x1E6E0300) & 0x000A0000;
1710 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1712 ast_moutdwm(ast, 0x1E6E0060, 0x00000005);
1716 ast_moutdwm(ast, 0x1E6E0060, 0x00000006);
1726 static void check_dram_size_2500(struct ast_device *ast, u32 tRFC)
1730 reg_04 = ast_mindwm(ast, 0x1E6E0004) & 0xfffffffc;
1731 reg_14 = ast_mindwm(ast, 0x1E6E0014) & 0xffffff00;
1733 ast_moutdwm(ast, 0xA0100000, 0x41424344);
1734 ast_moutdwm(ast, 0x90100000, 0x35363738);
1735 ast_moutdwm(ast, 0x88100000, 0x292A2B2C);
1736 ast_moutdwm(ast, 0x80100000, 0x1D1E1F10);
1739 if (ast_mindwm(ast, 0xA0100000) == 0x41424344) {
1743 } else if (ast_mindwm(ast, 0x90100000) == 0x35363738) {
1747 } else if (ast_mindwm(ast, 0x88100000) == 0x292A2B2C) {
1753 ast_moutdwm(ast, 0x1E6E0004, reg_04);
1754 ast_moutdwm(ast, 0x1E6E0014, reg_14);
1757 static void enable_cache_2500(struct ast_device *ast)
1761 reg_04 = ast_mindwm(ast, 0x1E6E0004);
1762 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x1000);
1765 data = ast_mindwm(ast, 0x1E6E0004);
1767 ast_moutdwm(ast, 0x1E6E0004, reg_04 | 0x400);
1770 static void set_mpll_2500(struct ast_device *ast)
1775 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1776 ast_moutdwm(ast, 0x1E6E0034, 0x00020080);
1778 ast_moutdwm(ast, addr, 0x0);
1781 ast_moutdwm(ast, 0x1E6E0034, 0x00020000);
1783 ast_moutdwm(ast, 0x1E6E2000, 0x1688A8A8);
1784 data = ast_mindwm(ast, 0x1E6E2070) & 0x00800000;
1788 ast_moutdwm(ast, 0x1E6E2160, 0x00011320);
1793 ast_moutdwm(ast, 0x1E6E2020, param);
1797 static void reset_mmc_2500(struct ast_device *ast)
1799 ast_moutdwm(ast, 0x1E78505C, 0x00000004);
1800 ast_moutdwm(ast, 0x1E785044, 0x00000001);
1801 ast_moutdwm(ast, 0x1E785048, 0x00004755);
1802 ast_moutdwm(ast, 0x1E78504C, 0x00000013);
1804 ast_moutdwm(ast, 0x1E785054, 0x00000077);
1805 ast_moutdwm(ast, 0x1E6E0000, 0xFC600309);
1808 static void ddr3_init_2500(struct ast_device *ast, const u32 *ddr_table)
1811 ast_moutdwm(ast, 0x1E6E0004, 0x00000303);
1812 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1813 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1814 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1815 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1816 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1817 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1818 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1821 ast_moutdwm(ast, 0x1E6E0200, 0x02492AAE);
1822 ast_moutdwm(ast, 0x1E6E0204, 0x00001001);
1823 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1824 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1825 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1826 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1827 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1828 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1829 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1830 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1831 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1832 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1833 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1834 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006);
1837 ast_moutdwm(ast, 0x1E6E0034, 0x00020091);
1840 ddr_phy_init_2500(ast);
1842 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1843 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1844 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1846 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1847 enable_cache_2500(ast);
1848 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1849 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1852 static void ddr4_init_2500(struct ast_device *ast, const u32 *ddr_table)
1859 ast_moutdwm(ast, 0x1E6E0004, 0x00000313);
1860 ast_moutdwm(ast, 0x1E6E0010, ddr_table[REGIDX_010]);
1861 ast_moutdwm(ast, 0x1E6E0014, ddr_table[REGIDX_014]);
1862 ast_moutdwm(ast, 0x1E6E0018, ddr_table[REGIDX_018]);
1863 ast_moutdwm(ast, 0x1E6E0020, ddr_table[REGIDX_020]); /* MODEREG4/6 */
1864 ast_moutdwm(ast, 0x1E6E0024, ddr_table[REGIDX_024]); /* MODEREG5 */
1865 ast_moutdwm(ast, 0x1E6E002C, ddr_table[REGIDX_02C] | 0x100); /* MODEREG0/2 */
1866 ast_moutdwm(ast, 0x1E6E0030, ddr_table[REGIDX_030]); /* MODEREG1/3 */
1869 ast_moutdwm(ast, 0x1E6E0200, 0x42492AAE);
1870 ast_moutdwm(ast, 0x1E6E0204, 0x09002000);
1871 ast_moutdwm(ast, 0x1E6E020C, 0x55E00B0B);
1872 ast_moutdwm(ast, 0x1E6E0210, 0x20000000);
1873 ast_moutdwm(ast, 0x1E6E0214, ddr_table[REGIDX_214]);
1874 ast_moutdwm(ast, 0x1E6E02E0, ddr_table[REGIDX_2E0]);
1875 ast_moutdwm(ast, 0x1E6E02E4, ddr_table[REGIDX_2E4]);
1876 ast_moutdwm(ast, 0x1E6E02E8, ddr_table[REGIDX_2E8]);
1877 ast_moutdwm(ast, 0x1E6E02EC, ddr_table[REGIDX_2EC]);
1878 ast_moutdwm(ast, 0x1E6E02F0, ddr_table[REGIDX_2F0]);
1879 ast_moutdwm(ast, 0x1E6E02F4, ddr_table[REGIDX_2F4]);
1880 ast_moutdwm(ast, 0x1E6E02F8, ddr_table[REGIDX_2F8]);
1881 ast_moutdwm(ast, 0x1E6E0290, 0x00100008);
1882 ast_moutdwm(ast, 0x1E6E02C4, 0x3C183C3C);
1883 ast_moutdwm(ast, 0x1E6E02C8, 0x00631E0E);
1886 ast_moutdwm(ast, 0x1E6E0034, 0x0001A991);
1894 ast_moutdwm(ast, 0x1E6E02C0, 0x00001C06);
1896 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1897 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1898 ast_moutdwm(ast, 0x1E6E02CC, phy_vref | (phy_vref << 8));
1900 ddr_phy_init_2500(ast);
1901 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1902 if (cbr_test_2500(ast)) {
1904 data = ast_mindwm(ast, 0x1E6E03D0);
1917 ast_moutdwm(ast, 0x1E6E02CC, min_phy_vref | (min_phy_vref << 8));
1927 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1928 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1929 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1931 ddr_phy_init_2500(ast);
1932 ast_moutdwm(ast, 0x1E6E000C, 0x00005C01);
1933 if (cbr_test_2500(ast)) {
1944 ast_moutdwm(ast, 0x1E6E000C, 0x00000000);
1945 ast_moutdwm(ast, 0x1E6E0060, 0x00000000);
1947 ast_moutdwm(ast, 0x1E6E02C0, 0x00000006 | (ddr_vref << 8));
1950 ddr_phy_init_2500(ast);
1952 ast_moutdwm(ast, 0x1E6E0120, ddr_table[REGIDX_PLL]);
1953 ast_moutdwm(ast, 0x1E6E000C, 0x42AA5C81);
1954 ast_moutdwm(ast, 0x1E6E0034, 0x0001AF93);
1956 check_dram_size_2500(ast, ddr_table[REGIDX_RFC]);
1957 enable_cache_2500(ast);
1958 ast_moutdwm(ast, 0x1E6E001C, 0x00000008);
1959 ast_moutdwm(ast, 0x1E6E0038, 0xFFFFFF00);
1962 static bool ast_dram_init_2500(struct ast_device *ast)
1970 set_mpll_2500(ast);
1971 reset_mmc_2500(ast);
1972 ddr_init_common_2500(ast);
1974 data = ast_mindwm(ast, 0x1E6E2070);
1976 ddr4_init_2500(ast, ast2500_ddr4_1600_timing_table);
1978 ddr3_init_2500(ast, ast2500_ddr3_1600_timing_table);
1979 } while (!ddr_test_2500(ast));
1981 ast_moutdwm(ast, 0x1E6E2040, ast_mindwm(ast, 0x1E6E2040) | 0x41);
1984 data = ast_mindwm(ast, 0x1E6E200C) & 0xF9FFFFFF;
1985 ast_moutdwm(ast, 0x1E6E200C, data | 0x10000000);
1990 void ast_patch_ahb_2500(struct ast_device *ast)
1995 ast_moutdwm(ast, 0x1e600000, 0xAEED1A03);
1996 ast_moutdwm(ast, 0x1e600084, 0x00010000);
1997 ast_moutdwm(ast, 0x1e600088, 0x00000000);
1998 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
1999 data = ast_mindwm(ast, 0x1e6e2070);
2012 ast_moutdwm(ast, 0x1E785004, 0x00000010);
2013 ast_moutdwm(ast, 0x1E785008, 0x00004755);
2014 ast_moutdwm(ast, 0x1E78500c, 0x00000033);
2018 ast_moutdwm(ast, 0x1e6e2000, 0x1688A8A8);
2019 data = ast_mindwm(ast, 0x1e6e2000);
2021 ast_moutdwm(ast, 0x1e6e207c, 0x08000000); /* clear fast reset */
2026 struct ast_device *ast = to_ast_device(dev);
2030 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);
2033 ast_patch_ahb_2500(ast);
2036 ast_moutdwm(ast, 0x1E78502C, 0x00000000);
2037 ast_moutdwm(ast, 0x1E78504C, 0x00000000);
2052 ast_moutdwm(ast, 0x1E6E2090, 0x20000000);
2053 ast_moutdwm(ast, 0x1E6E2094, 0x00004000);
2054 if (ast_mindwm(ast, 0x1E6E2070) & 0x00800000) {
2055 ast_moutdwm(ast, 0x1E6E207C, 0x00800000);
2057 ast_moutdwm(ast, 0x1E6E2070, 0x00800000);
2060 temp = ast_mindwm(ast, 0x1E6E2070);
2062 ast_moutdwm(ast, 0x1E6E207C, 0x00004000);
2065 temp = ast_read32(ast, 0x12008);
2067 ast_write32(ast, 0x12008, temp);
2069 if (!ast_dram_init_2500(ast))
2072 temp = ast_mindwm(ast, 0x1e6e2040);
2073 ast_moutdwm(ast, 0x1e6e2040, temp | 0x40);
2078 reg = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd0, 0xff);