Lines Matching refs:adj
199 const struct drm_display_mode *mode, struct drm_display_mode *adj)
209 drm_mode_set_crtcinfo(adj, CRTC_INTERLACE_HALVE_V);
215 if (armada_drm_crtc_mode_valid(crtc, adj) != MODE_OK)
219 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL);
331 struct drm_display_mode *adj = &crtc->state->adjusted_mode;
337 bool interlaced = !!(adj->flags & DRM_MODE_FLAG_INTERLACE);
340 rm = adj->crtc_hsync_start - adj->crtc_hdisplay;
341 lm = adj->crtc_htotal - adj->crtc_hsync_end;
342 bm = adj->crtc_vsync_start - adj->crtc_vdisplay;
343 tm = adj->crtc_vtotal - adj->crtc_vsync_end;
346 crtc->base.id, crtc->name, DRM_MODE_ARG(adj));
350 dcrtc->variant->compute_clock(dcrtc, adj, &sclk);
358 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 |
359 adj->crtc_htotal;
361 val = adj->crtc_hsync_start;
366 val -= adj->crtc_htotal / 2;
375 val = adj->crtc_vdisplay << 16 | adj->crtc_hdisplay;
388 val = adj->flags & DRM_MODE_FLAG_NVSYNC ? CFG_VSYNC_INV : 0;
400 if (adj->flags & DRM_MODE_FLAG_NCSYNC)
402 if (adj->flags & DRM_MODE_FLAG_NHSYNC)
404 if (adj->flags & DRM_MODE_FLAG_NVSYNC)