Lines Matching refs:hwdev
270 static int malidp500_query_hw(struct malidp_hw_device *hwdev)
272 u32 conf = malidp_hw_read(hwdev, MALIDP500_CONFIG_ID);
276 hwdev->min_line_size = 2;
277 hwdev->max_line_size = SZ_2K * ln_size_mult;
278 hwdev->rotation_memory[0] = SZ_1K * 64 * ln_size_mult;
279 hwdev->rotation_memory[1] = 0; /* no second rotation memory bank */
284 static void malidp500_enter_config_mode(struct malidp_hw_device *hwdev)
288 malidp_hw_setbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
290 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
303 static void malidp500_leave_config_mode(struct malidp_hw_device *hwdev)
307 malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
308 malidp_hw_clearbits(hwdev, MALIDP500_DC_CONFIG_REQ, MALIDP500_DC_CONTROL);
310 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
319 static bool malidp500_in_config_mode(struct malidp_hw_device *hwdev)
323 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
330 static void malidp500_set_config_valid(struct malidp_hw_device *hwdev, u8 value)
333 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
335 malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP500_CONFIG_VALID);
338 static void malidp500_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
342 malidp_hw_write(hwdev, hwdev->output_color_depth,
343 hwdev->hw->map.out_depth_base);
344 malidp_hw_clearbits(hwdev, MALIDP500_DC_CLEAR_MASK, MALIDP500_DC_CONTROL);
350 malidp_hw_setbits(hwdev, val, MALIDP500_DC_CONTROL);
360 malidp_hw_write(hwdev, val, MALIDP500_BGND_COLOR);
361 malidp_hw_write(hwdev, MALIDP_BGND_COLOR_B, MALIDP500_BGND_COLOR + 4);
365 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
369 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
373 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
376 malidp_hw_write(hwdev, val, MALIDP500_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
379 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
381 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
387 if (hwdev->arqos_value) {
388 val = hwdev->arqos_value;
389 malidp_hw_setbits(hwdev, val, MALIDP500_RQOS_QUALITY);
417 static int malidp500_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
430 static void malidp500_se_write_pp_coefftab(struct malidp_hw_device *hwdev,
438 malidp_hw_write(hwdev,
442 malidp_hw_write(hwdev, MALIDP_SE_SET_COEFFTAB_DATA(
447 static int malidp500_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
461 malidp500_se_write_pp_coefftab(hwdev,
467 malidp500_se_write_pp_coefftab(hwdev,
471 malidp500_se_write_pp_coefftab(hwdev,
479 static long malidp500_se_calc_mclk(struct malidp_hw_device *hwdev,
503 ret = clk_get_rate(hwdev->mclk);
512 static int malidp500_enable_memwrite(struct malidp_hw_device *hwdev,
518 u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
521 malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC);
524 if (hwdev->mw_state != MW_NOT_ENABLED)
525 hwdev->mw_state = MW_RESTART;
527 hwdev->mw_state = MW_START;
529 malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT);
532 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
533 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
534 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
537 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
538 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
539 malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE);
545 malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h),
552 malidp_hw_write(hwdev, rgb2yuv_coeffs[i],
557 malidp_hw_setbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL);
562 static void malidp500_disable_memwrite(struct malidp_hw_device *hwdev)
564 u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
566 if (hwdev->mw_state == MW_START || hwdev->mw_state == MW_RESTART)
567 hwdev->mw_state = MW_STOP;
568 malidp_hw_clearbits(hwdev, MALIDP_SE_MEMWRITE_EN, MALIDP500_SE_CONTROL);
569 malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC);
572 static int malidp550_query_hw(struct malidp_hw_device *hwdev)
574 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
577 hwdev->min_line_size = 2;
581 hwdev->max_line_size = SZ_2K;
586 hwdev->max_line_size = SZ_4K;
591 hwdev->max_line_size = 1280;
597 hwdev->max_line_size = 0;
601 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
605 static void malidp550_enter_config_mode(struct malidp_hw_device *hwdev)
609 malidp_hw_setbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
611 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
624 static void malidp550_leave_config_mode(struct malidp_hw_device *hwdev)
628 malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
629 malidp_hw_clearbits(hwdev, MALIDP550_DC_CONFIG_REQ, MALIDP550_DC_CONTROL);
631 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
640 static bool malidp550_in_config_mode(struct malidp_hw_device *hwdev)
644 status = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_REG_STATUS);
651 static void malidp550_set_config_valid(struct malidp_hw_device *hwdev, u8 value)
654 malidp_hw_setbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
656 malidp_hw_clearbits(hwdev, MALIDP_CFG_VALID, MALIDP550_CONFIG_VALID);
659 static void malidp550_modeset(struct malidp_hw_device *hwdev, struct videomode *mode)
663 malidp_hw_write(hwdev, hwdev->output_color_depth,
664 hwdev->hw->map.out_depth_base);
665 malidp_hw_write(hwdev, val, MALIDP550_DE_CONTROL);
678 malidp_hw_write(hwdev, val, MALIDP550_DE_BGND_COLOR);
682 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_H_TIMINGS);
686 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_V_TIMINGS);
694 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_SYNC_WIDTH);
697 malidp_hw_write(hwdev, val, MALIDP550_TIMINGS_BASE + MALIDP_DE_HV_ACTIVE);
700 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
702 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_ILACED, MALIDP_DE_DISPLAY_FUNC);
759 static int malidp550_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
786 static int malidp650_rotmem_required(struct malidp_hw_device *hwdev, u16 w,
806 static int malidp550_se_set_scaling_coeffs(struct malidp_hw_device *hwdev,
815 malidp_hw_clearbits(hwdev, mask, MALIDP550_SE_CONTROL);
816 malidp_hw_setbits(hwdev, new_value, MALIDP550_SE_CONTROL);
820 static long malidp550_se_calc_mclk(struct malidp_hw_device *hwdev,
844 ret = clk_get_rate(hwdev->mclk);
853 static int malidp550_enable_memwrite(struct malidp_hw_device *hwdev,
859 u32 de_base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
862 malidp_hw_setbits(hwdev, MALIDP_SCALE_ENGINE_EN, de_base + MALIDP_DE_DISPLAY_FUNC);
864 hwdev->mw_state = MW_ONESHOT;
866 malidp_hw_write(hwdev, fmt_id, base + MALIDP_MW_FORMAT);
869 malidp_hw_write(hwdev, lower_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_LOW);
870 malidp_hw_write(hwdev, upper_32_bits(addrs[1]), base + MALIDP_MW_P2_PTR_HIGH);
871 malidp_hw_write(hwdev, pitches[1], base + MALIDP_MW_P2_STRIDE);
874 malidp_hw_write(hwdev, lower_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_LOW);
875 malidp_hw_write(hwdev, upper_32_bits(addrs[0]), base + MALIDP_MW_P1_PTR_HIGH);
876 malidp_hw_write(hwdev, pitches[0], base + MALIDP_MW_P1_STRIDE);
882 malidp_hw_write(hwdev, MALIDP_DE_H_ACTIVE(w) | MALIDP_DE_V_ACTIVE(h),
884 malidp_hw_setbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN,
891 malidp_hw_write(hwdev, rgb2yuv_coeffs[i],
899 static void malidp550_disable_memwrite(struct malidp_hw_device *hwdev)
901 u32 base = malidp_get_block_base(hwdev, MALIDP_DE_BLOCK);
903 malidp_hw_clearbits(hwdev, MALIDP550_SE_MEMWRITE_ONESHOT | MALIDP_SE_MEMWRITE_EN,
905 malidp_hw_clearbits(hwdev, MALIDP_SCALE_ENGINE_EN, base + MALIDP_DE_DISPLAY_FUNC);
908 static int malidp650_query_hw(struct malidp_hw_device *hwdev)
910 u32 conf = malidp_hw_read(hwdev, MALIDP550_CONFIG_ID);
913 hwdev->min_line_size = 4;
919 hwdev->max_line_size = 0;
922 hwdev->max_line_size = SZ_4K;
927 hwdev->max_line_size = 2560;
932 hwdev->rotation_memory[0] = hwdev->rotation_memory[1] = rsize * SZ_1K;
1158 static void malidp_hw_clear_irq(struct malidp_hw_device *hwdev, u8 block, u32 irq)
1160 u32 base = malidp_get_block_base(hwdev, block);
1162 if (hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ)
1163 malidp_hw_write(hwdev, irq, base + MALIDP_REG_CLEARIRQ);
1165 malidp_hw_write(hwdev, irq, base + MALIDP_REG_STATUS);
1172 struct malidp_hw_device *hwdev;
1178 hwdev = malidp->dev;
1179 hw = hwdev->hw;
1187 if (hwdev->pm_suspended)
1191 dc_status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
1193 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, dc_status);
1205 status = malidp_hw_read(hwdev, MALIDP_REG_STATUS);
1209 mask = malidp_hw_read(hwdev, MALIDP_REG_MASKIRQ);
1221 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, status);
1236 void malidp_de_irq_hw_init(struct malidp_hw_device *hwdev)
1239 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
1240 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
1241 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
1242 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
1245 malidp_hw_enable_irq(hwdev, MALIDP_DC_BLOCK,
1246 hwdev->hw->map.dc_irq_map.irq_mask);
1249 malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
1250 hwdev->hw->map.de_irq_map.irq_mask);
1256 struct malidp_hw_device *hwdev = malidp->dev;
1260 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
1261 malidp_hw_clear_irq(hwdev, MALIDP_DE_BLOCK, 0xffffffff);
1262 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
1263 malidp_hw_clear_irq(hwdev, MALIDP_DC_BLOCK, 0xffffffff);
1273 malidp_de_irq_hw_init(hwdev);
1278 void malidp_de_irq_fini(struct malidp_hw_device *hwdev)
1280 malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
1281 hwdev->hw->map.de_irq_map.irq_mask);
1282 malidp_hw_disable_irq(hwdev, MALIDP_DC_BLOCK,
1283 hwdev->hw->map.dc_irq_map.irq_mask);
1290 struct malidp_hw_device *hwdev = malidp->dev;
1291 struct malidp_hw *hw = hwdev->hw;
1300 if (hwdev->pm_suspended)
1303 status = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_STATUS);
1312 mask = malidp_hw_read(hwdev, hw->map.se_base + MALIDP_REG_MASKIRQ);
1316 switch (hwdev->mw_state) {
1323 hwdev->mw_state = MW_NOT_ENABLED;
1330 hw->disable_memwrite(hwdev);
1336 status = malidp_hw_read(hwdev, hw->map.dc_base + MALIDP_REG_STATUS);
1339 hw->set_config_valid(hwdev, 1);
1344 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, status);
1349 void malidp_se_irq_hw_init(struct malidp_hw_device *hwdev)
1352 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
1353 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
1355 malidp_hw_enable_irq(hwdev, MALIDP_SE_BLOCK,
1356 hwdev->hw->map.se_irq_map.irq_mask);
1367 struct malidp_hw_device *hwdev = malidp->dev;
1371 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
1372 malidp_hw_clear_irq(hwdev, MALIDP_SE_BLOCK, 0xffffffff);
1382 hwdev->mw_state = MW_NOT_ENABLED;
1383 malidp_se_irq_hw_init(hwdev);
1388 void malidp_se_irq_fini(struct malidp_hw_device *hwdev)
1390 malidp_hw_disable_irq(hwdev, MALIDP_SE_BLOCK,
1391 hwdev->hw->map.se_irq_map.irq_mask);