Lines Matching refs:hwdev
43 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
54 malidp_hw_write(hwdev, gamma_write_mask,
55 hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
57 malidp_hw_write(hwdev, data[i],
58 hwdev->hw->map.coeffs_base +
66 struct malidp_hw_device *hwdev = malidp->dev;
72 malidp_hw_clearbits(hwdev,
81 malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
83 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
93 struct malidp_hw_device *hwdev = malidp->dev;
100 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
109 malidp_hw_write(hwdev,
111 hwdev->hw->map.coeffs_base +
114 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
125 struct malidp_hw_device *hwdev = malidp->dev;
128 u32 se_control = hwdev->hw->map.se_base +
129 ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
137 val = malidp_hw_read(hwdev, se_control);
139 malidp_hw_write(hwdev, val, se_control);
143 hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
144 val = malidp_hw_read(hwdev, se_control);
151 malidp_hw_write(hwdev, val, se_control);
156 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
159 malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
162 malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
163 malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
164 malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
165 malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
174 struct malidp_hw_device *hwdev = malidp->dev;
177 hwdev->hw->set_config_valid(hwdev, 1);
179 if (hwdev->hw->in_config_mode(hwdev)) {
398 struct malidp_hw_device *hwdev = malidp->dev;
404 drm->mode_config.min_width = hwdev->min_line_size;
405 drm->mode_config.min_height = hwdev->min_line_size;
406 drm->mode_config.max_width = hwdev->max_line_size;
407 drm->mode_config.max_height = hwdev->max_line_size;
428 struct malidp_hw_device *hwdev = malidp->dev;
448 malidp_de_irq_fini(hwdev);
593 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
606 core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
619 core_id = malidp_hw_read(hwdev,
670 struct malidp_hw_device *hwdev = malidp->dev;
673 WARN_ON(!hwdev->hw->in_config_mode(hwdev));
675 malidp_se_irq_fini(hwdev);
676 malidp_de_irq_fini(hwdev);
677 hwdev->pm_suspended = true;
678 clk_disable_unprepare(hwdev->mclk);
679 clk_disable_unprepare(hwdev->aclk);
680 clk_disable_unprepare(hwdev->pclk);
689 struct malidp_hw_device *hwdev = malidp->dev;
691 clk_prepare_enable(hwdev->pclk);
692 clk_prepare_enable(hwdev->aclk);
693 clk_prepare_enable(hwdev->mclk);
694 hwdev->pm_suspended = false;
695 malidp_de_irq_hw_init(hwdev);
696 malidp_se_irq_hw_init(hwdev);
706 struct malidp_hw_device *hwdev;
721 hwdev = drmm_kzalloc(drm, sizeof(*hwdev), GFP_KERNEL);
722 if (!hwdev)
725 hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
726 malidp->dev = hwdev;
728 hwdev->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
729 if (IS_ERR(hwdev->regs))
730 return PTR_ERR(hwdev->regs);
732 hwdev->pclk = devm_clk_get(dev, "pclk");
733 if (IS_ERR(hwdev->pclk))
734 return PTR_ERR(hwdev->pclk);
736 hwdev->aclk = devm_clk_get(dev, "aclk");
737 if (IS_ERR(hwdev->aclk))
738 return PTR_ERR(hwdev->aclk);
740 hwdev->mclk = devm_clk_get(dev, "mclk");
741 if (IS_ERR(hwdev->mclk))
742 return PTR_ERR(hwdev->mclk);
744 hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
745 if (IS_ERR(hwdev->pxlclk))
746 return PTR_ERR(hwdev->pxlclk);
776 if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
781 ret = hwdev->hw->query_hw(hwdev);
787 version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
795 &hwdev->arqos_value);
797 hwdev->arqos_value = 0x0;
808 malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
809 hwdev->output_color_depth = out_depth;
863 malidp_se_irq_fini(hwdev);
864 malidp_de_irq_fini(hwdev);
887 struct malidp_hw_device *hwdev = malidp->dev;
893 malidp_se_irq_fini(hwdev);
894 malidp_de_irq_fini(hwdev);