Lines Matching refs:hdlcd
40 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
43 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
49 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
50 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
52 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask | HDLCD_INTERRUPT_VSYNC);
59 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
60 unsigned int mask = hdlcd_read(hdlcd, HDLCD_REG_INT_MASK);
62 hdlcd_write(hdlcd, HDLCD_REG_INT_MASK, mask & ~HDLCD_INTERRUPT_VSYNC);
84 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
102 hdlcd_write(hdlcd, HDLCD_REG_PIXEL_FORMAT, (btpp - 1) << 3);
114 hdlcd_write(hdlcd, HDLCD_REG_RED_SELECT, format->red.offset |
119 hdlcd_write(hdlcd, HDLCD_REG_GREEN_SELECT, format->green.offset |
121 hdlcd_write(hdlcd, HDLCD_REG_BLUE_SELECT, format->blue.offset |
129 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
149 hdlcd_write(hdlcd, HDLCD_REG_BUS_OPTIONS,
152 hdlcd_write(hdlcd, HDLCD_REG_V_DATA, m->crtc_vdisplay - 1);
153 hdlcd_write(hdlcd, HDLCD_REG_V_BACK_PORCH, vm.vback_porch - 1);
154 hdlcd_write(hdlcd, HDLCD_REG_V_FRONT_PORCH, vm.vfront_porch - 1);
155 hdlcd_write(hdlcd, HDLCD_REG_V_SYNC, vm.vsync_len - 1);
156 hdlcd_write(hdlcd, HDLCD_REG_H_DATA, m->crtc_hdisplay - 1);
157 hdlcd_write(hdlcd, HDLCD_REG_H_BACK_PORCH, vm.hback_porch - 1);
158 hdlcd_write(hdlcd, HDLCD_REG_H_FRONT_PORCH, vm.hfront_porch - 1);
159 hdlcd_write(hdlcd, HDLCD_REG_H_SYNC, vm.hsync_len - 1);
160 hdlcd_write(hdlcd, HDLCD_REG_POLARITIES, polarities);
166 clk_set_rate(hdlcd->clk, m->crtc_clock * 1000);
172 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
174 clk_prepare_enable(hdlcd->clk);
176 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 1);
183 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
186 hdlcd_write(hdlcd, HDLCD_REG_COMMAND, 0);
187 clk_disable_unprepare(hdlcd->clk);
193 struct hdlcd_drm_private *hdlcd = crtc_to_hdlcd_priv(crtc);
196 rate = clk_round_rate(hdlcd->clk, clk_rate);
267 struct hdlcd_drm_private *hdlcd;
277 hdlcd = drm_to_hdlcd_priv(plane->dev);
278 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_LENGTH, fb->pitches[0]);
279 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_PITCH, fb->pitches[0]);
280 hdlcd_write(hdlcd, HDLCD_REG_FB_LINE_COUNT, dest_h - 1);
281 hdlcd_write(hdlcd, HDLCD_REG_FB_BASE, scanout_start);
299 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
314 hdlcd->plane = plane;
321 struct hdlcd_drm_private *hdlcd = drm_to_hdlcd_priv(drm);
329 ret = drm_crtc_init_with_planes(drm, &hdlcd->crtc, primary, NULL,
334 drm_crtc_helper_add(&hdlcd->crtc, &hdlcd_crtc_helper_funcs);