Lines Matching defs:UCHAR
48 #ifndef UCHAR
49 typedef unsigned char UCHAR;
211 UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
212 UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
237 UCHAR ucExtendedFunctionCode;
238 UCHAR ucReserved;
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
260 UCHAR ucExtendedFunctionCode;
261 UCHAR ucReserved;
441 UCHAR ucAction; //0:reserved //1:Memory //2:Engine
442 UCHAR ucReserved; //may expand to return larger Fbdiv later
443 UCHAR ucFbDiv; //return value
444 UCHAR ucPostDiv; //return value
450 UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
452 UCHAR ucPostDiv; //return post div to be written to register
500 UCHAR ucRefDiv; //Output Parameter
501 UCHAR ucPostDiv; //Output Parameter
502 UCHAR ucCntlFlag; //Output Parameter
503 UCHAR ucReserved;
533 UCHAR ucRefDiv; //Output Parameter
534 UCHAR ucPostDiv; //Output Parameter
537 UCHAR ucCntlFlag; //Output Flags
538 UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
540 UCHAR ucReserved;
560 UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
561 UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
562 UCHAR ucPllCntlFlag; //Output Flags: control flag
563 UCHAR ucReserved;
585 UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
586 UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
587 UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
588 UCHAR ucSscEnable;
608 UCHAR ucDllSpeed; //Output
609 UCHAR ucPostDiv; //Output
611 UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
612 UCHAR ucPllCntlFlag; //Output:
614 UCHAR ucBWCntl;
664 UCHAR ucMclkDPMState;
665 UCHAR ucReserved[3];
755 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
756 UCHAR ucPadding[3];
765 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
766 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
767 UCHAR ucPadding[2];
772 UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
773 UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
774 UCHAR ucPadding[2];
783 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
784 UCHAR ucPadding[3];
794 UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
795 UCHAR ucMisc; //Valid only when table revision =1.3 and above
813 UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
814 UCHAR ucAction; // 0: turn off encoder
829 UCHAR ucConfig;
837 UCHAR ucAction; // =0: turn off encoder
839 UCHAR ucEncoderMode;
845 UCHAR ucLaneNum; // how many lanes to enable
846 UCHAR ucReserved[2];
889 UCHAR ucReserved1:2;
890 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
891 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
892 UCHAR ucReserved:1;
893 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
895 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
896 UCHAR ucReserved:1;
897 UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
898 UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
899 UCHAR ucReserved1:2;
908 UCHAR ucAction;
909 UCHAR ucEncoderMode;
915 UCHAR ucLaneNum; // how many lanes to enable
916 UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
917 UCHAR ucReserved;
962 UCHAR ucReserved1:1;
963 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
964 UCHAR ucReserved:3;
965 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
967 UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
968 UCHAR ucReserved:3;
969 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
970 UCHAR ucReserved1:1;
989 UCHAR ucAction;
991 UCHAR ucEncoderMode;
998 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1003 UCHAR ucLaneNum; // how many lanes to enable
1004 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1005 UCHAR ucReserved;
1015 UCHAR ucReserved1:1;
1016 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1017 UCHAR ucReserved:2;
1018 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1020 UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
1021 UCHAR ucReserved:2;
1022 UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
1023 UCHAR ucReserved1:1;
1046 UCHAR ucConfig;
1048 UCHAR ucAction;
1050 UCHAR ucEncoderMode;
1057 UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
1062 UCHAR ucLaneNum; // how many lanes to enable
1063 UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
1064 UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
1083 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1084 UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP
1085 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1086 UCHAR ucLaneNum; // Lane number
1088 UCHAR ucBitPerColor;
1089 UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
1090 UCHAR ucReserved[2];
1095 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1096 UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP
1097 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1098 UCHAR ucLaneNum; // Lane number
1100 UCHAR ucHPDSel;
1101 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1102 UCHAR ucReserved[2];
1107 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1108 UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP
1109 UCHAR ucPanelMode; // =0: external DP
1112 UCHAR ucReserved;
1118 UCHAR ucDigId; // 0~6 map to DIG0~DIG6
1119 UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
1120 UCHAR ucReserved[2];
1150 UCHAR ucLaneSel;
1151 UCHAR ucLaneSet;
1162 UCHAR ucConfig;
1176 UCHAR ucAction; // =0: turn off encoder
1178 UCHAR ucReserved[4];
1231 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1234 UCHAR ucReserved:1;
1235 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1236 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1237 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1240 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1241 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1243 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1244 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1245 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1247 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
1248 UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
1249 UCHAR ucReserved:1;
1250 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1291 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1292 UCHAR ucReserved[4];
1298 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1301 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1302 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1303 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1305 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1306 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1308 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1309 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1310 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1312 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1313 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1314 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1330 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1331 UCHAR ucLaneNum;
1332 UCHAR ucReserved[3];
1373 UCHAR ucLaneSel;
1376 UCHAR ucLaneSet;
1379 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1380 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1381 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1383 UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
1384 UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
1385 UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
1394 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1397 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1398 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1399 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1401 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1402 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1404 UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
1405 UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
1406 UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
1408 UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
1409 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
1410 UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
1427 UCHAR ucConfig;
1429 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
1430 UCHAR ucLaneNum;
1431 UCHAR ucReserved[3];
1463 UCHAR ucReservd1:1;
1464 UCHAR ucHPDSel:3;
1465 UCHAR ucPhyClkSrcId:2;
1466 UCHAR ucCoherentMode:1;
1467 UCHAR ucReserved:1;
1469 UCHAR ucReserved:1;
1470 UCHAR ucCoherentMode:1;
1471 UCHAR ucPhyClkSrcId:2;
1472 UCHAR ucHPDSel:3;
1473 UCHAR ucReservd1:1;
1480 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1481 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1482 UCHAR ucLaneNum; // indicate lane number 1-8
1483 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1484 UCHAR ucDigMode; // indicate DIG mode
1487 UCHAR ucConfig;
1489 UCHAR ucDigEncoderSel; // indicate DIG front end encoder
1490 UCHAR ucDPLaneSet;
1491 UCHAR ucReserved;
1492 UCHAR ucReserved1;
1561 UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
1562 UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
1565 UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
1566 UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
1568 UCHAR ucLaneNum; // Lane number
1570 UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
1571 UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
1572 UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
1573 UCHAR ucReserved;
1616 UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
1617 UCHAR ucAction; //
1618 UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
1619 UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
1620 UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
1621 UCHAR ucReserved;
1659 UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
1664 UCHAR aucPadding[3]; // padding to DWORD aligned
1704 UCHAR ucAction;
1705 UCHAR ucBriLevel;
1716 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1717 UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
1731 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1732 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
1733 UCHAR ucPadding[2];
1746 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1747 UCHAR ucPadding[3];
1756 UCHAR ucH_Replication; // horizontal replication
1757 UCHAR ucV_Replication; // vertical replication
1758 UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1759 UCHAR ucPadding;
1768 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1769 UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
1770 UCHAR ucPadding[2];
1776 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1777 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1778 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1779 UCHAR ucPadding;
1805 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
1806 UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
1807 UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
1808 UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
1823 UCHAR ucPostDiv; // post divider
1824 UCHAR ucFracFbDiv; // fractional feedback divider
1825 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1826 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1827 UCHAR ucCRTC; // Which CRTC uses this Ppll
1828 UCHAR ucPadding;
1843 UCHAR ucPostDiv; // post divider
1844 UCHAR ucFracFbDiv; // fractional feedback divider
1845 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1846 UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
1847 UCHAR ucCRTC; // Which CRTC uses this Ppll
1848 UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
1890 UCHAR ucPostDiv; // post divider
1891 UCHAR ucFracFbDiv; // fractional feedback divider
1892 UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
1893 UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
1896 UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
1897 UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
1899 UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
1910 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
1913 UCHAR ucReserved;
1914 UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
1919 UCHAR ucPostDiv; // post divider.
1920 UCHAR ucRefDiv; // Reference divider
1921 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1922 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1924 UCHAR ucEncoderMode; // Encoder mode:
1925 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
1967 UCHAR ucPostDiv; // post divider.
1968 UCHAR ucRefDiv; // Reference divider
1969 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
1970 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
1972 UCHAR ucEncoderMode; // Encoder mode:
1973 UCHAR ucMiscInfo; // bit[0]= Force program PPLL
2005 UCHAR ucStatus;
2006 UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
2007 UCHAR ucReserved[2];
2019 UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
2020 UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
2022 UCHAR ucEncoderMode; // Encoder mode:
2023 UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
2029 UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
2030 UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
2031 UCHAR ucReserved[2];
2055 UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
2056 UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
2057 UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
2058 UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
2077 UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
2078 UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
2079 UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
2080 UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
2117 UCHAR ucTransmitterID;
2118 UCHAR ucEncodeMode;
2121 UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
2122 UCHAR ucConfig; //if none DVO, not defined yet
2124 UCHAR ucReserved[3];
2133 UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
2134 UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
2135 UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
2136 UCHAR ucExtTransmitterID; // external encoder id.
2137 UCHAR ucReserved[2];
2156 UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
2157 UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
2158 UCHAR ucReserved[2];
2175 UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
2176 UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
2177 UCHAR ucPadding[2];
2210 UCHAR ucSlaveAddr; //Read from which slave
2211 UCHAR ucLineNumber; //Read from which HW assisted line
2232 UCHAR ucData; //PS data1
2233 UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
2234 UCHAR ucSlaveAddr; //Write to which slave
2235 UCHAR ucLineNumber; //Write from which HW assisted line
2243 UCHAR ucSlaveAddr; //Write to which slave
2244 UCHAR ucLineNumber; //Write from which HW assisted line
2256 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2257 UCHAR ucPwrBehaviorId;
2263 UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
2264 UCHAR ucReserved;
2278 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2279 UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
2280 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2281 UCHAR ucPadding[3];
2288 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2289 UCHAR ucSpreadSpectrumStep; //
2290 UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
2291 UCHAR ucSpreadSpectrumDelay;
2292 UCHAR ucSpreadSpectrumRange;
2293 UCHAR ucPadding;
2300 UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
2301 UCHAR ucSpreadSpectrumStep; //
2302 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2303 UCHAR ucSpreadSpectrumDelay;
2304 UCHAR ucSpreadSpectrumRange;
2305 UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
2311 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2315 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2336 UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
2340 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
2403 UCHAR ucMisc; // bit0=0: Enable single link
2407 UCHAR ucAction; // 0: turn off encoder
2423 UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
2424 UCHAR ucAction; // 0: turn off encoder
2426 UCHAR ucTruncate; // bit0=0: Disable truncate
2430 UCHAR ucSpatial; // bit0=0: Disable spatial dithering
2434 UCHAR ucTemporal; // bit0=0: Disable temporal dithering
2440 UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
2473 UCHAR ucEnable; // Enable or Disable External TMDS encoder
2474 UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
2475 UCHAR ucPadding[2];
2513 UCHAR ucDVOConfig;
2514 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2515 UCHAR ucReseved[4];
2522 UCHAR ucDVOConfig;
2523 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
2524 UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
2525 UCHAR ucReseved[3];
2598 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2599 UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
2600 UCHAR ucVoltageIndex; // An index to tell which voltage level
2601 UCHAR ucReserved;
2606 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
2607 UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
2614 UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2615 UCHAR ucVoltageMode; // Indicate action: Set voltage level
2670 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2671 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2709 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2710 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2731 UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
2732 UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
2766 UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
2767 UCHAR ucAction; // 0: turn off encoder
2843 UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
2844 UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
2845 UCHAR ucVideoPortInfo; // Provides the video port capabilities
2846 UCHAR ucHostPortInfo; // Provides host port configuration information
2857 UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
2858 UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
2859 UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
2860 UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
2861 UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
2862 UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
2863 UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
2864 UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2865 UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2866 UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2867 UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2868 UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
2961 UCHAR ucASICMaxTemperature;
2962 UCHAR ucPadding[3]; //Don't use them
2977 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
2978 UCHAR ucDesign_ID; //Indicate what is the board design
2979 UCHAR ucMemoryModule_ID; //Indicate what is the board design
2995 UCHAR ucASICMaxTemperature;
2996 UCHAR ucMinAllowedBL_Level;
2997 UCHAR ucPadding[2]; //Don't use them
3013 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3014 UCHAR ucDesign_ID; //Indicate what is the board design
3015 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3031 UCHAR ucASICMaxTemperature;
3032 UCHAR ucMinAllowedBL_Level;
3033 UCHAR ucPadding[2]; //Don't use them
3050 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3051 UCHAR ucDesign_ID; //Indicate what is the board design
3052 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3068 UCHAR ucASICMaxTemperature;
3069 UCHAR ucMinAllowedBL_Level;
3088 UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
3089 UCHAR ucDesign_ID; //Indicate what is the board design
3090 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3107 UCHAR ucReserved1; //Was ucASICMaxTemperature;
3108 UCHAR ucMinAllowedBL_Level;
3128 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3129 UCHAR ucReserved4[3];
3139 UCHAR ucEMBEDDED_CAP:2; // Bit[1:0] Embedded feature level
3140 UCHAR ucReserved:2; // Bit[3:2] Reserved
3141 UCHAR ucBRANDING_ID:4; // Bit[7:4] Branding ID
3157 UCHAR ucReserved3; //Was ucASICMaxTemperature;
3158 UCHAR ucMinAllowedBL_Level;
3164 UCHAR ucRemoteDisplayConfig;
3165 UCHAR ucReserved5[3]; //Was usMinEngineClockPLL_Input and usMaxEngineClockPLL_Input
3176 UCHAR ucMemoryModule_ID; //Indicate what is the board design
3177 UCHAR ucCoolingSolution_ID; //0: Air cooling; 1: Liquid cooling ... [COOLING_SOLUTION]
3179 UCHAR ucReserved9;
3207 UCHAR ucNumberOfCyclesInPeriodHi;
3208 UCHAR ucLCDTimingSel; //=0:not valid.!=0 sel this timing descriptor from LCD EDID.
3222 UCHAR ucMaxNBVoltage;
3223 UCHAR ucMinNBVoltage;
3224 UCHAR ucMemoryType; //[7:4]=1:DDR1;=2:DDR2;=3:DDR3.[3:0] is reserved
3225 UCHAR ucNumberOfCyclesInPeriod; //CG.FVTHROT_PWM_CTRL_REG0.NumberOfCyclesInPeriod
3226 UCHAR ucStartingPWM_HighTime; //CG.FVTHROT_PWM_CTRL_REG0.StartingPWM_HighTime
3227 UCHAR ucHTLinkWidth; //16 bit vs. 8 bit
3228 UCHAR ucMaxNBVoltageHigh;
3229 UCHAR ucMinNBVoltageHigh;
3286 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3287 UCHAR ucUMAChannelNumber;
3288 UCHAR ucDockingPinBit;
3289 UCHAR ucDockingPinPolarity;
3462 UCHAR ucHtcTmpLmt; //bit [22:16] of D24F3x64 Hardware Thermal Control (HTC) Register, may not be needed, TBD
3463 UCHAR ucTjOffset; //bit [28:22] of D24F3xE4 Thermtrip Status Register,may not be needed, TBD
3470 UCHAR ucMemoryType; //[3:0]=1:DDR1;=2:DDR2;=3:DDR3.[7:4] is reserved
3471 UCHAR ucUMAChannelNumber;
3661 UCHAR bfHW_Capable:1;
3662 UCHAR bfHW_EngineID:3;
3663 UCHAR bfI2C_LineMux:4;
3665 UCHAR bfI2C_LineMux:4;
3666 UCHAR bfHW_EngineID:3;
3667 UCHAR bfHW_Capable:1;
3674 UCHAR ucAccess;
3692 UCHAR ucClkMaskShift;
3693 UCHAR ucClkEnShift;
3694 UCHAR ucClkY_Shift;
3695 UCHAR ucClkA_Shift;
3696 UCHAR ucDataMaskShift;
3697 UCHAR ucDataEnShift;
3698 UCHAR ucDataY_Shift;
3699 UCHAR ucDataA_Shift;
3700 UCHAR ucReserved1;
3701 UCHAR ucReserved2;
3810 UCHAR ucH_Border; // From DFP EDID
3811 UCHAR ucV_Border;
3812 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3813 UCHAR ucPadding[3];
3830 UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
3831 UCHAR ucOverscanRight; // right
3832 UCHAR ucOverscanLeft; // left
3833 UCHAR ucOverscanBottom; // bottom
3834 UCHAR ucOverscanTop; // top
3835 UCHAR ucReserved;
3862 UCHAR ucInternalModeNumber;
3863 UCHAR ucRefreshRate;
3879 UCHAR ucHBorder;
3880 UCHAR ucVBorder;
3882 UCHAR ucInternalModeNumber;
3883 UCHAR ucRefreshRate;
3905 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3906 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3907 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3911 UCHAR ucPanelDefaultRefreshRate;
3912 UCHAR ucPanelIdentification;
3913 UCHAR ucSS_Id;
3925 UCHAR ucPowerSequenceDigOntoDEin10Ms;
3926 UCHAR ucPowerSequenceDEtoBLOnin10Ms;
3927 UCHAR ucLVDS_Misc; // Bit0:{=0:single, =1:dual},Bit1 {=0:666RGB, =1:888RGB},Bit2:3:{Grey level}
3931 UCHAR ucPanelDefaultRefreshRate;
3932 UCHAR ucPanelIdentification;
3933 UCHAR ucSS_Id;
3936 UCHAR ucLCDPanel_SpecialHandlingCap;
3937 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
3938 UCHAR ucReserved[2];
3978 UCHAR ucSupportedRefreshRate;
3979 UCHAR ucMinRefreshRateForDRR;
3999 UCHAR ucLCD_Misc; // Reorganized in V13
4005 UCHAR ucPanelDefaultRefreshRate;
4006 UCHAR ucPanelIdentification;
4007 UCHAR ucSS_Id;
4010 UCHAR ucLCDPanel_SpecialHandlingCap; // Reorganized in V13
4015 UCHAR ucPanelInfoSize; // start from ATOM_DTD_FORMAT to end of panel info, include ExtInfoTable
4018 UCHAR ucPowerSequenceDIGONtoDE_in4Ms;
4019 UCHAR ucPowerSequenceDEtoVARY_BL_in4Ms;
4020 UCHAR ucPowerSequenceVARY_BLtoDE_in4Ms;
4021 UCHAR ucPowerSequenceDEtoDIGON_in4Ms;
4023 UCHAR ucOffDelay_in4Ms;
4024 UCHAR ucPowerSequenceVARY_BLtoBLON_in4Ms;
4025 UCHAR ucPowerSequenceBLONtoVARY_BL_in4Ms;
4026 UCHAR ucReserved1;
4028 UCHAR ucDPCD_eDP_CONFIGURATION_CAP; // dpcd 0dh
4029 UCHAR ucDPCD_MAX_LINK_RATE; // dpcd 01h
4030 UCHAR ucDPCD_MAX_LANE_COUNT; // dpcd 02h
4031 UCHAR ucDPCD_MAX_DOWNSPREAD; // dpcd 03h
4034 UCHAR uceDPToLVDSRxId;
4035 UCHAR ucLcdReservd;
4082 UCHAR ucRecordType;
4089 UCHAR ucRecordType;
4090 UCHAR ucRTSValue;
4097 UCHAR ucRecordType;
4108 UCHAR ucRecordType;
4109 UCHAR ucFakeEDIDLength; // = 128 means EDID length is 128 bytes, otherwise the EDID length = ucFakeEDIDLength*128
4110 UCHAR ucFakeEDIDString[]; // This actually has ucFakeEdidLength elements.
4115 UCHAR ucRecordType;
4135 UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Bit2=1: PCIE REFCLK SS =0 iternal PPLL SS Others:TBD
4136 UCHAR ucSS_Step;
4137 UCHAR ucSS_Delay;
4138 UCHAR ucSS_Id;
4139 UCHAR ucRecommendedRef_Div;
4140 UCHAR ucSS_Range; //it was reserved for V11
4198 UCHAR ucTV_SuppportedStandard;
4199 UCHAR ucTV_BootUpDefaultStandard;
4200 UCHAR ucExt_TV_ASIC_ID;
4201 UCHAR ucExt_TV_ASIC_SlaveAddr;
4207 UCHAR ucRevisionNumber; //10h : Revision 1.0; 11h : Revision 1.1
4208 UCHAR ucMaxLinkRate; //06h : 1.62Gbps per lane; 0Ah = 2.7Gbps per lane
4209 UCHAR ucMaxLane; //Bits 4:0 = MAX_LANE_COUNT (1/2/4). Bit 7 = ENHANCED_FRAME_CAP
4210 UCHAR ucMaxDownSpread; //Bit0 = 0: No Down spread; Bit0 = 1: 0.5% (Subject to change according to DP spec)
4364 UCHAR ucGpioPinBitShift;
4365 UCHAR ucGPIO_ID;
4406 UCHAR ucSettings;
4407 UCHAR ucReserved;
4449 UCHAR ucBitShift;
4450 UCHAR ucPinActiveState; //ucPinActiveState: Bit0=1 active high, =0 active low
4452 UCHAR ucMiscInfo;
4453 UCHAR uc480i;
4454 UCHAR uc480p;
4455 UCHAR uc720p;
4456 UCHAR uc1080i;
4457 UCHAR ucLetterBoxMode;
4458 UCHAR ucReserved[3];
4459 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4469 UCHAR ucMiscInfo;
4470 UCHAR uc480i;
4471 UCHAR uc480p;
4472 UCHAR uc720p;
4473 UCHAR uc1080i;
4474 UCHAR ucReserved;
4475 UCHAR ucLetterBoxMode;
4476 UCHAR ucNumOfWbGpioBlocks; //For Component video D-Connector support. If zere, NTSC type connector
4530 UCHAR ucNumOfDispPath;
4531 UCHAR ucVersion;
4532 UCHAR ucPadding[2];
4546 UCHAR ucNumberOfObjects;
4547 UCHAR ucPadding[3];
4553 UCHAR ucNumberOfSrc;
4555 UCHAR ucNumberOfDst;
4591 UCHAR ucDP_Lane3_Source:2;
4592 UCHAR ucDP_Lane2_Source:2;
4593 UCHAR ucDP_Lane1_Source:2;
4594 UCHAR ucDP_Lane0_Source:2;
4596 UCHAR ucDP_Lane0_Source:2;
4597 UCHAR ucDP_Lane1_Source:2;
4598 UCHAR ucDP_Lane2_Source:2;
4599 UCHAR ucDP_Lane3_Source:2;
4611 UCHAR ucDVI_CLK_Source:2;
4612 UCHAR ucDVI_DATA0_Source:2;
4613 UCHAR ucDVI_DATA1_Source:2;
4614 UCHAR ucDVI_DATA2_Source:2;
4616 UCHAR ucDVI_DATA2_Source:2;
4617 UCHAR ucDVI_DATA1_Source:2;
4618 UCHAR ucDVI_DATA0_Source:2;
4619 UCHAR ucDVI_CLK_Source:2;
4628 UCHAR ucExtAUXDDCLutIndex; //An index into external AUX/DDC channel LUT
4629 UCHAR ucExtHPDPINLutIndex; //An index into external HPD pin LUT
4632 UCHAR ucChannelMapping; // if ucChannelMapping=0, using default one to one mapping
4636 UCHAR ucChPNInvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
4658 UCHAR ucGuid [NUMBER_OF_UCHAR_FOR_GUID]; // a GUID is a 16 byte long string
4660 UCHAR ucChecksum; // a simple Checksum of the sum of whole structure equal to 0x0.
4661 UCHAR uc3DStereoPinId; // use for eDP panel
4662 UCHAR ucRemoteDisplayConfig;
4663 UCHAR uceDPToLVDSRxId;
4664 UCHAR ucFixDPVoltageSwing; // usCaps[1]=1, this indicate DP_LANE_SET value
4665 UCHAR Reserved[3]; // for potential expansion
4671 UCHAR ucRecordType; //An emun to indicate the record type
4672 UCHAR ucRecordSize; //The size of the whole record in byte
4706 UCHAR ucI2CAddr; //The slave address, it's 0 when the record is attached to connector for DDC
4712 UCHAR ucHPDIntGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4713 UCHAR ucPlugged_PinState;
4720 UCHAR ucProtectionFlag;
4721 UCHAR ucReserved;
4734 UCHAR ucNumberOfDevice;
4735 UCHAR ucReserved;
4743 UCHAR ucConfigGPIOID;
4744 UCHAR ucConfigGPIOState; //Set to 1 when it's active high to enable external flow in
4745 UCHAR ucFlowinGPIPID;
4746 UCHAR ucExtInGPIPID;
4752 UCHAR ucCTL1GPIO_ID;
4753 UCHAR ucCTL1GPIOState; //Set to 1 when it's active high
4754 UCHAR ucCTL2GPIO_ID;
4755 UCHAR ucCTL2GPIOState; //Set to 1 when it's active high
4756 UCHAR ucCTL3GPIO_ID;
4757 UCHAR ucCTL3GPIOState; //Set to 1 when it's active high
4758 UCHAR ucCTLFPGA_IN_ID;
4759 UCHAR ucPadding[3];
4765 UCHAR ucGPIOID; //Corresponding block in GPIO_PIN_INFO table gives the pin info
4766 UCHAR ucTVActiveState; //Indicating when the pin==0 or 1 when TV is connected
4772 UCHAR ucTMSGPIO_ID;
4773 UCHAR ucTMSGPIOState; //Set to 1 when it's active high
4774 UCHAR ucTCKGPIO_ID;
4775 UCHAR ucTCKGPIOState; //Set to 1 when it's active high
4776 UCHAR ucTDOGPIO_ID;
4777 UCHAR ucTDOGPIOState; //Set to 1 when it's active high
4778 UCHAR ucTDIGPIO_ID;
4779 UCHAR ucTDIGPIOState; //Set to 1 when it's active high
4780 UCHAR ucPadding[2];
4787 UCHAR ucGPIOID; // GPIO_ID, find the corresponding ID in GPIO_LUT table
4788 UCHAR ucGPIO_PinState; // Pin state showing how to set-up the pin
4794 UCHAR ucFlags; // Future expnadibility
4795 UCHAR ucNumberOfPins; // Number of GPIO pins used to control the object
4827 UCHAR ucPadding[2];
4889 UCHAR ucFlowCntlGpioId;
4890 UCHAR ucSwapCntlGpioId;
4891 UCHAR ucConnectedDvoBundle;
4892 UCHAR ucPadding;
4904 UCHAR ucSubConnectorType; //CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D|X_ID_DUAL_LINK_DVI_D|HDMI_TYPE_A
4905 UCHAR ucReserved;
4912 UCHAR ucMuxType; //decide the number of ucMuxState, =0, no pin state, =1: single state with complement, >1: multiple state
4913 UCHAR ucMuxControlPin;
4914 UCHAR ucMuxState[2]; //for alligment purpose
4920 UCHAR ucMuxType;
4921 UCHAR ucMuxControlPin;
4922 UCHAR ucMuxState[2]; //for alligment purpose
4932 UCHAR ucHPDPINMap[MAX_NUMBER_OF_EXT_HPDPIN_LUT_ENTRIES]; //An fixed size array which maps external pins to internal GPIO_PIN_INFO table
4958 UCHAR ucMaxTmdsClkRateIn2_5Mhz;
4959 UCHAR ucReserved;
4966 UCHAR ucConnectorType;
4967 UCHAR ucPosition;
4981 UCHAR ucLength;
4982 UCHAR ucWidth;
4983 UCHAR ucConnNum;
4984 UCHAR ucReserved;
4996 UCHAR ucNumOfVoltageEntries;
4997 UCHAR ucBytesPerVoltageEntry;
4998 UCHAR ucVoltageStep; //Indicating in how many mv increament is one step, 0.5mv unit
4999 UCHAR ucDefaultVoltageEntry;
5000 UCHAR ucVoltageControlI2cLine;
5001 UCHAR ucVoltageControlAddress;
5002 UCHAR ucVoltageControlOffset;
5009 UCHAR ucVoltageEntries[64]; //64 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries*ucBytesPerVoltageEntry
5017 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5018 UCHAR ucFlag; // bit0=0 :step is 1mv =1 0.5mv
5019 UCHAR ucBaseVID; // if there is no lookup table, VID= BaseVID + ( Vol - BaseLevle ) /VoltageStep
5020 UCHAR ucReserved;
5021 UCHAR ucVIDAdjustEntries[32]; // 32 is for allocation, the actual number of entry is present at ucNumOfVoltageEntries
5032 UCHAR ucNumOfVoltageEntries; // Number of Voltage Entry, which indicate max Voltage
5033 UCHAR ucReserved[3];
5039 UCHAR ucVoltageControlId; //Indicate it is controlled by I2C or GPIO or HW state machine
5040 UCHAR ucVoltageControlI2cLine;
5041 UCHAR ucVoltageControlAddress;
5042 UCHAR ucVoltageControlOffset;
5044 UCHAR ucGpioPinBitShift[9]; //at most 8 pin support 255 VIDs, termintate with 0xff
5045 UCHAR ucReserved;
5077 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5078 UCHAR ucSize; //Size of Object
5085 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5086 UCHAR ucSize; //Size of Object
5105 UCHAR ucLeakageId;
5106 UCHAR ucReserved;
5111 UCHAR ucVoltageType; //Indicate Voltage Source: VDDC, MVDDC, MVDDQ or MVDDCI
5112 UCHAR ucVoltageMode; //Indicate voltage control mode: Init/Set/Leakage/Set phase
5143 UCHAR ucVoltageRegulatorId; //Indicate Voltage Regulator Id
5144 UCHAR ucVoltageControlI2cLine;
5145 UCHAR ucVoltageControlAddress;
5146 UCHAR ucVoltageControlOffset;
5147 UCHAR ucVoltageControlFlag; // Bit0: 0 - One byte data; 1 - Two byte data
5148 UCHAR ulReserved[3];
5159 UCHAR ucVoltageGpioCntlId; // default is 0 which indicate control through CG VID mode
5160 UCHAR ucGpioEntryNum; // indiate the entry numbers of Votlage/Gpio value Look up table
5161 UCHAR ucPhaseDelay; // phase delay in unit of micro second
5162 UCHAR ucReserved;
5170 UCHAR ucLeakageCntlId; // default is 0
5171 UCHAR ucLeakageEntryNum; // indicate the entry number of LeakageId/Voltage Lut table
5172 UCHAR ucReserved[2];
5188 UCHAR ucSVDGpioId; //0~31 indicate GPIO0~31
5189 UCHAR ucSVCGpioId; //0~31 indicate GPIO0~31
5198 UCHAR ucMergedVType; // VDDC/VDCCI/....
5199 UCHAR ucReserved[3];
5207 UCHAR ucDPMTblVIndex; // Voltage Index in SMC_DPM_Table structure VddcTable/VddGfxTable
5208 UCHAR ucDPMState; // DPMState0~7
5236 UCHAR ucProfileId;
5237 UCHAR ucReserved;
5258 UCHAR ucLeakageBinNum; // indicate the entry number of LeakageId/Voltage Lut table
5261 UCHAR ucElbVDDC_Num;
5265 UCHAR ucElbVDDCI_Num;
5276 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5277 UCHAR ucEfuseLength; // Efuse bits length,
5286 UCHAR ucEfuseBitLSB; // Efuse bit LSB in DWORD address, for example Index 911, usEfuseBitLSB= 911-112*8=15
5287 UCHAR ucEfuseLength; // Efuse bits length,
5310 UCHAR ucLkgEfuseBitLSB;
5311 UCHAR ucLkgEfuseLength;
5351 UCHAR ucLkgEfuseBitLSB;
5352 UCHAR ucLkgEfuseLength;
5393 UCHAR ucLkgEfuseBitLSB;
5394 UCHAR ucLkgEfuseLength;
5452 UCHAR ucLkgEfuseBitLSB;
5453 UCHAR ucLkgEfuseLength;
5487 UCHAR ucSM_A0_sign;
5488 UCHAR ucSM_A1_sign;
5489 UCHAR ucSM_A2_sign;
5490 UCHAR ucSM_A3_sign;
5491 UCHAR ucSM_A4_sign;
5492 UCHAR ucSM_A5_sign;
5493 UCHAR ucSM_A6_sign;
5494 UCHAR ucSM_A7_sign;
5514 UCHAR ucLkgEfuseBitLSB; //Efuse Lkg_FT bit shift in 32bit DWORD
5515 UCHAR ucLkgEfuseLength; //Efuse Lkg_FT length
5531 UCHAR ucSM_A0_sign; //def="EVV_SM_A0_SIGN" descr="=0 SM_A0 is postive. =1: SM_A0 is negative" unit="1"/>
5532 UCHAR ucSM_A1_sign; //def="EVV_SM_A1_SIGN" descr="=0 SM_A1 is postive. =1: SM_A1 is negative" unit="1"/>
5533 UCHAR ucSM_A2_sign; //def="EVV_SM_A2_SIGN" descr="=0 SM_A2 is postive. =1: SM_A2 is negative" unit="1"/>
5534 UCHAR ucSM_A3_sign; //def="EVV_SM_A3_SIGN" descr="=0 SM_A3 is postive. =1: SM_A3 is negative" unit="1"/>
5535 UCHAR ucSM_A4_sign; //def="EVV_SM_A4_SIGN" descr="=0 SM_A4 is postive. =1: SM_A4 is negative" unit="1"/>
5536 UCHAR ucSM_A5_sign; //def="EVV_SM_A5_SIGN" descr="=0 SM_A5 is postive. =1: SM_A5 is negative" unit="1"/>
5537 UCHAR ucSM_A6_sign; //def="EVV_SM_A6_SIGN" descr="=0 SM_A6 is postive. =1: SM_A6 is negative" unit="1"/>
5538 UCHAR ucSM_A7_sign; //def="EVV_SM_A7_SIGN" descr="=0 SM_A7 is postive. =1: SM_A7 is negative" unit="1"/>
5558 UCHAR ucLkgEfuseBitLSB;
5559 UCHAR ucLkgEfuseLength;
5575 UCHAR ucSM_A0_sign;
5576 UCHAR ucSM_A1_sign;
5577 UCHAR ucSM_A2_sign;
5578 UCHAR ucSM_A3_sign;
5579 UCHAR ucSM_A4_sign;
5580 UCHAR ucSM_A5_sign;
5581 UCHAR ucSM_A6_sign;
5582 UCHAR ucSM_A7_sign;
5614 UCHAR ucEnableGB_VDROOP_TABLE_CKSOFF;
5615 UCHAR ucEnableGB_VDROOP_TABLE_CKSON;
5616 UCHAR ucEnableGB_FUSE_TABLE_CKSOFF;
5617 UCHAR ucEnableGB_FUSE_TABLE_CKSON;
5619 UCHAR ucEnableApplyAVFS_CKS_OFF_Voltage;
5620 UCHAR ucReserved;
5626 UCHAR ucVco_setting; // 1: 3-6GHz, 3: 2-4GHz
5627 UCHAR ucPostdiv; // divide by 2^n
5638 UCHAR ucSclkEntryNum; // for potential future extend, indicate the number of ATOM_SCLK_FCW_RANGE_ENTRY_V1
5639 UCHAR ucSMUVer;
5640 UCHAR ucSharePowerSource;
5641 UCHAR ucReserved;
5650 UCHAR GfxIpMinVer;
5651 UCHAR GfxIpMajVer;
5652 UCHAR max_shader_engines;
5653 UCHAR max_tile_pipes;
5654 UCHAR max_cu_per_sh;
5655 UCHAR max_sh_per_se;
5656 UCHAR max_backends_per_se;
5657 UCHAR max_texture_channel_caches;
5663 UCHAR GfxIpMinVer;
5664 UCHAR GfxIpMajVer;
5665 UCHAR max_shader_engines;
5666 UCHAR max_tile_pipes;
5667 UCHAR max_cu_per_sh;
5668 UCHAR max_sh_per_se;
5669 UCHAR max_backends_per_se;
5670 UCHAR max_texture_channel_caches;
5679 UCHAR ucPwrSrcId; // Power source
5680 UCHAR ucPwrSensorType; // GPIO, I2C or none
5681 UCHAR ucPwrSensId; // if GPIO detect, it is GPIO id, if I2C detect, it is I2C id
5682 UCHAR ucPwrSensSlaveAddr; // Slave address if I2C detect
5683 UCHAR ucPwrSensRegIndex; // I2C register Index if I2C detect
5684 UCHAR ucPwrSensRegBitMask; // detect which bit is used if I2C detect
5685 UCHAR ucPwrSensActiveState; // high active or low active
5686 UCHAR ucReserve[3]; // reserve
5693 UCHAR asPwrbehave[16];
5746 UCHAR ucHtcTmpLmt;
5747 UCHAR ucHtcHystLmt;
5756 UCHAR ucMemoryType;
5757 UCHAR ucUMAChannelNumber;
5780 UCHAR ulBoostVid_2bit;
5781 UCHAR EnableBoost;
5784 UCHAR ucLvdsMisc;
5785 UCHAR ucLVDSReserved;
5944 UCHAR ucHtcTmpLmt;
5945 UCHAR ucHtcHystLmt;
5954 UCHAR ucMemoryType;
5955 UCHAR ucUMAChannelNumber;
5956 UCHAR strVBIOSMsg[40];
5978 UCHAR ulBoostVid_2bit;
5979 UCHAR EnableBoost;
5982 UCHAR ucLvdsMisc;
5983 UCHAR ucTravisLVDSVolAdjust;
5984 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
5985 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
5986 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
5987 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
5988 UCHAR ucLVDSOffToOnDelay_in4Ms;
5989 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
5990 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
5991 UCHAR ucMinAllowedBL_Level;
5997 UCHAR ucNBDPMEnable;
5998 UCHAR ucReserved[3];
5999 UCHAR ucDPMState0VclkFid;
6000 UCHAR ucDPMState0DclkFid;
6001 UCHAR ucDPMState1VclkFid;
6002 UCHAR ucDPMState1DclkFid;
6003 UCHAR ucDPMState2VclkFid;
6004 UCHAR ucDPMState2DclkFid;
6005 UCHAR ucDPMState3VclkFid;
6006 UCHAR ucDPMState3DclkFid;
6176 UCHAR ucHtcTmpLmt;
6177 UCHAR ucHtcHystLmt;
6185 UCHAR ucMemoryType;
6186 UCHAR ucUMAChannelNumber;
6187 UCHAR strVBIOSMsg[40];
6209 UCHAR ucLvdsMisc;
6210 UCHAR ucTravisLVDSVolAdjust;
6211 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6212 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6213 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6214 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6215 UCHAR ucLVDSOffToOnDelay_in4Ms;
6216 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6217 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6218 UCHAR ucMinAllowedBL_Level;
6377 UCHAR ucI2cRegIndex;
6378 UCHAR ucI2cRegVal;
6394 UCHAR ucHtcTmpLmt;
6395 UCHAR ucHtcHystLmt;
6403 UCHAR ucMemoryType;
6404 UCHAR ucUMAChannelNumber;
6405 UCHAR strVBIOSMsg[40];
6407 UCHAR ucExtHDMIReDrvSlvAddr;
6408 UCHAR ucExtHDMIReDrvRegNum;
6430 UCHAR ucLvdsMisc;
6431 UCHAR ucTravisLVDSVolAdjust;
6432 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6433 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6434 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6435 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6436 UCHAR ucLVDSOffToOnDelay_in4Ms;
6437 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6438 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6439 UCHAR ucMinAllowedBL_Level;
6446 UCHAR ucEDPv1_4VSMode;
6447 UCHAR ucReserved2;
6474 UCHAR ucProfileID; // SENSOR_PROFILES
6485 UCHAR ucID; // 0: Rear, 1: Front right of user, 2: Front left of user
6486 UCHAR strModuleName[8];
6492 UCHAR ucID; // 0: Rear, 1: Front
6493 UCHAR strName[8];
6517 UCHAR ucHtcTmpLmt;
6518 UCHAR ucHtcHystLmt;
6526 UCHAR ucMemoryType;
6527 UCHAR ucUMAChannelNumber;
6550 UCHAR ucLvdsMisc;
6551 UCHAR ucTravisLVDSVolAdjust;
6552 UCHAR ucLVDSPwrOnSeqDIGONtoDE_in4Ms;
6553 UCHAR ucLVDSPwrOnSeqDEtoVARY_BL_in4Ms;
6554 UCHAR ucLVDSPwrOffSeqVARY_BLtoDE_in4Ms;
6555 UCHAR ucLVDSPwrOffSeqDEtoDIGON_in4Ms;
6556 UCHAR ucLVDSOffToOnDelay_in4Ms;
6557 UCHAR ucLVDSPwrOnSeqVARY_BLtoBLON_in4Ms;
6558 UCHAR ucLVDSPwrOffSeqBLONtoVARY_BL_in4Ms;
6559 UCHAR ucMinAllowedBL_Level;
6567 UCHAR ucEDPv1_4VSMode;
6568 UCHAR ucReserved2;
6601 UCHAR ucNunberOfBytes; //Indicates how many bytes SW needs to write to the external ASIC for one block, besides to "Start" and "Stop"
6602 UCHAR ucI2CData[]; //I2C data in bytes, should be less than 16 bytes usually
6610 UCHAR ucSSChipID; //SS chip being used
6611 UCHAR ucSSChipSlaveAddr; //Slave Address to set up this SS chip
6612 UCHAR ucNumOfI2CDataRecords; //number of data block
6634 UCHAR ucClockIndication; //Indicate which clock source needs SS
6635 UCHAR ucSpreadSpectrumMode; //Bit1=0 Down Spread,=1 Center Spread.
6636 UCHAR ucReserved[2];
6660 UCHAR ucClockIndication; //Indicate which clock source needs SS
6661 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6662 UCHAR ucReserved[2];
6691 UCHAR ucClockIndication; //Indicate which clock source needs SS
6692 UCHAR ucSpreadSpectrumMode; //Bit0=0 Down Spread,=1 Center Spread, bit1=0: internal SS bit1=1: external SS
6693 UCHAR ucReserved[2];
7172 UCHAR ucAction; //not define yet
7173 UCHAR ucFbDiv_Hi; //Fbdiv Hi byte
7174 UCHAR ucFbDiv; //FB value
7175 UCHAR ucPostDiv; //Post div
7186 UCHAR ucGPIO_ID; //return value, read from GPIO pins
7187 UCHAR ucGPIOBitShift; //define which bit in uGPIOBitVal need to be update
7188 UCHAR ucGPIOBitVal; //Set/Reset corresponding bit defined in ucGPIOBitMask
7189 UCHAR ucAction; //=GPIO_PIN_WRITE: Read; =GPIO_PIN_READ: Write
7194 UCHAR ucScaler; // ATOM_SCALER1, ATOM_SCALER2
7195 UCHAR ucEnable; // ATOM_SCALER_DISABLE or ATOM_SCALER_CENTER or ATOM_SCALER_EXPANSION
7196 UCHAR ucTVStandard; //
7197 UCHAR ucPadding[1];
7210 UCHAR ucHWIconVertOffset; // Hardware Icon Vertical offset
7211 UCHAR ucHWIconHorzOffset; // Hardware Icon Horizontal offset
7212 UCHAR ucSelection; // ATOM_CURSOR1 or ATOM_ICON1 or ATOM_CURSOR2 or ATOM_ICON2
7213 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7226 UCHAR ucSurface; // Surface 1 or 2
7227 UCHAR ucPadding[3];
7234 UCHAR ucSurface; // Surface 1 or 2
7235 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7236 UCHAR ucPadding[2];
7243 UCHAR ucSurface; // Surface 1 or 2
7244 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7253 UCHAR ucColorDepth;
7254 UCHAR ucPixelFormat;
7255 UCHAR ucSurface; // Surface 1 or 2
7256 UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
7257 UCHAR ucModeType;
7258 UCHAR ucReserved;
7299 UCHAR ucLutId;
7300 UCHAR ucAction;
7314 UCHAR ucInterruptId;
7315 UCHAR ucServiceId;
7316 UCHAR ucStatus;
7317 UCHAR ucReserved;
7340 UCHAR ucBitShift;
7341 UCHAR ucBitLength;
7354 UCHAR IOAccessSequence[256];
7390 UCHAR ucVMode_Num; //Video mode number
7391 UCHAR ucTV_Mode_Num; //Internal TV mode number
7409 UCHAR ucTV_Mode_Num;
7441 UCHAR ucMemoryType;
7442 UCHAR ucMemoryVendor;
7443 UCHAR ucAdjMCId;
7444 UCHAR ucDynClkId;
7474 UCHAR ucPreRegDataLength; // offset in ATOM_INIT_REG_DATA_BLOCK.saRegDataBuf
7584 UCHAR ucRevision;
7585 UCHAR ucChecksum;
7586 UCHAR ucReserved1;
7587 UCHAR ucReserved2;
7605 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7606 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] reserved;
7607 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender
7608 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7609 UCHAR ucRow; // Number of Row,in power of 2;
7610 UCHAR ucColumn; // Number of Column,in power of 2;
7611 UCHAR ucBank; // Nunber of Bank;
7612 UCHAR ucRank; // Number of Rank, in power of 2
7613 UCHAR ucChannelNum; // Number of channel;
7614 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7615 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7616 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7617 UCHAR ucReserved[2];
7632 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7633 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7634 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7635 UCHAR ucMemoryDeviceCfg; // [7:4]=0x0:4M;=0x1:8M;=0x2:16M;0x3:32M....[3:0]=0x0:x4;=0x1:x8;=0x2:x16;=0x3:x32...
7636 UCHAR ucRow; // Number of Row,in power of 2;
7637 UCHAR ucColumn; // Number of Column,in power of 2;
7638 UCHAR ucBank; // Nunber of Bank;
7639 UCHAR ucRank; // Number of Rank, in power of 2
7640 UCHAR ucChannelNum; // Number of channel;
7641 UCHAR ucChannelConfig; // [3:0]=Indication of what channel combination;[4:7]=Channel bit width, in number of 2
7642 UCHAR ucDefaultMVDDQ_ID; // Default MVDDQ setting for this memory block, ID linking to MVDDQ info table to find real set-up data;
7643 UCHAR ucDefaultMVDDC_ID; // Default MVDDC setting for this memory block, ID linking to MVDDC info table to find real set-up data;
7644 UCHAR ucRefreshRateFactor;
7645 UCHAR ucReserved[3];
7660 UCHAR ucCL; // CAS latency
7661 UCHAR ucWL; // WRITE Latency
7662 UCHAR uctRAS; // tRAS
7663 UCHAR uctRC; // tRC
7664 UCHAR uctRFC; // tRFC
7665 UCHAR uctRCDR; // tRCDR
7666 UCHAR uctRCDW; // tRCDW
7667 UCHAR uctRP; // tRP
7668 UCHAR uctRRD; // tRRD
7669 UCHAR uctWR; // tWR
7670 UCHAR uctWTR; // tWTR
7671 UCHAR uctPDIX; // tPDIX
7672 UCHAR uctFAW; // tFAW
7673 UCHAR uctAOND; // tAOND
7677 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7678 UCHAR ucReserved;
7690 UCHAR ucCL; // CAS latency
7691 UCHAR ucWL; // WRITE Latency
7692 UCHAR uctRAS; // tRAS
7693 UCHAR uctRC; // tRC
7694 UCHAR uctRFC; // tRFC
7695 UCHAR uctRCDR; // tRCDR
7696 UCHAR uctRCDW; // tRCDW
7697 UCHAR uctRP; // tRP
7698 UCHAR uctRRD; // tRRD
7699 UCHAR uctWR; // tWR
7700 UCHAR uctWTR; // tWTR
7701 UCHAR uctPDIX; // tPDIX
7702 UCHAR uctFAW; // tFAW
7703 UCHAR uctAOND; // tAOND
7704 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7706 UCHAR uctCCDL; //
7707 UCHAR uctCRCRL; //
7708 UCHAR uctCRCWL; //
7709 UCHAR uctCKE; //
7710 UCHAR uctCKRSE; //
7711 UCHAR uctCKRSX; //
7712 UCHAR uctFAW32; //
7713 UCHAR ucMR5lo; //
7714 UCHAR ucMR5hi; //
7715 UCHAR ucTerminator;
7726 UCHAR ucCL; // CAS latency
7727 UCHAR ucWL; // WRITE Latency
7728 UCHAR uctRAS; // tRAS
7729 UCHAR uctRC; // tRC
7730 UCHAR uctRFC; // tRFC
7731 UCHAR uctRCDR; // tRCDR
7732 UCHAR uctRCDW; // tRCDW
7733 UCHAR uctRP; // tRP
7734 UCHAR uctRRD; // tRRD
7735 UCHAR uctWR; // tWR
7736 UCHAR uctWTR; // tWTR
7737 UCHAR uctPDIX; // tPDIX
7738 UCHAR uctFAW; // tFAW
7739 UCHAR uctAOND; // tAOND
7740 UCHAR ucflag; // flag to control memory timing calculation. bit0= control EMRS2 Infineon
7742 UCHAR uctCCDL; //
7743 UCHAR uctCRCRL; //
7744 UCHAR uctCRCWL; //
7745 UCHAR uctCKE; //
7746 UCHAR uctCKRSE; //
7747 UCHAR uctCKRSX; //
7748 UCHAR uctFAW32; //
7749 UCHAR ucMR4lo; //
7750 UCHAR ucMR4hi; //
7751 UCHAR ucMR5lo; //
7752 UCHAR ucMR5hi; //
7753 UCHAR ucTerminator;
7754 UCHAR ucReserved;
7769 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4;[3:0] - must not be used for now;
7770 UCHAR ucMemoryVenderID; // Predefined,never change across designs or memory type/vender. If not predefined, vendor detection table gets executed
7771 UCHAR ucRow; // Number of Row,in power of 2;
7772 UCHAR ucColumn; // Number of Column,in power of 2;
7773 UCHAR ucBank; // Nunber of Bank;
7774 UCHAR ucRank; // Number of Rank, in power of 2
7775 UCHAR ucBurstSize; // burst size, 0= burst size=4 1= burst size=8
7776 UCHAR ucDllDisBit; // position of DLL Enable/Disable bit in EMRS ( Extended Mode Register )
7777 UCHAR ucRefreshRateFactor; // memory refresh rate in unit of ms
7778 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7779 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7780 UCHAR ucMemAttrib; // Memory Device Addribute, like RDBI/WDBI etc
7791 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7792 UCHAR ucChannelNum; // board dependent parameter:Number of channel;
7793 UCHAR ucChannelSize; // board dependent parameter:32bit or 64bit
7794 UCHAR ucVREFI; // board dependnt parameter: EXT or INT +160mv to -140mv
7795 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7796 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7814 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7815 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7816 UCHAR ucChannelNum; // Number of channels present in this module config
7817 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7818 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7819 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7820 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7821 UCHAR ucVREFI; // board dependent parameter
7822 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7823 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7824 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7826 UCHAR ucReserved[3];
7837 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7838 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7839 UCHAR ucReserved2[2];
7856 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7857 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7858 UCHAR ucChannelNum; // Number of channels present in this module config
7859 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7860 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7861 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7862 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7863 UCHAR ucVREFI; // board dependent parameter
7864 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7865 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7866 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7868 UCHAR ucReserved[3];
7873 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7874 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7875 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7876 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7888 UCHAR ucExtMemoryID; // An external indicator (by hardcode, callback or pin) to tell what is the current memory module
7889 UCHAR ucMemoryType; // [7:4]=0x1:DDR1;=0x2:DDR2;=0x3:DDR3;=0x4:DDR4; 0x5:DDR5 [3:0] - Must be 0x0 for now;
7890 UCHAR ucChannelNum; // Number of channels present in this module config
7891 UCHAR ucChannelWidth; // 0 - 32 bits; 1 - 64 bits
7892 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7893 UCHAR ucFlag; // To enable/disable functionalities based on memory type
7894 UCHAR ucMisc; // bit0: 0 - single rank; 1 - dual rank; bit2: 0 - burstlength 4, 1 - burstlength 8
7895 UCHAR ucVREFI; // board dependent parameter
7896 UCHAR ucNPL_RT; // board dependent parameter:NPL round trip delay, used for calculate memory timing parameters
7897 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7898 UCHAR ucMemorySize; // BIOS internal reserved space to optimize code size, updated by the compiler, shouldn't be modified manually!!
7900 UCHAR ucReserved[3];
7905 UCHAR ucMemoryVenderID; // Predefined, If not predefined, vendor detection table gets executed
7906 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7907 UCHAR ucFIFODepth; // FIFO depth supposes to be detected during vendor detection, but if we dont do vendor detection we have to hardcode FIFO Depth
7908 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7919 UCHAR ucExtMemoryID; // Current memory module ID
7920 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7921 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7922 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7923 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7924 UCHAR ucReserve; // In MC7x, the lower 4 bits are used as bit8-11 of memory size. In other MC code, it's not used.
7925 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7926 UCHAR ucVREFI; // Not used.
7927 UCHAR ucNPL_RT; // Round trip delay (MC_SEQ_CAS_TIMING [28:24]:TCL=CL+NPL_RT-2). Always 2.
7928 UCHAR ucPreamble; // [7:4] Write Preamble, [3:0] Read Preamble
7929 UCHAR ucMemorySize; // Total memory size in unit of 16MB for CONFIG_MEMSIZE - bit[23:0] zeros
7931 UCHAR ucReserved;
7935 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7936 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7937 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7938 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7950 UCHAR ucExtMemoryID; // Current memory module ID
7951 UCHAR ucMemoryType; // MEM_TYPE_DDR2/DDR3/GDDR3/GDDR5
7952 UCHAR ucChannelNum; // Number of mem. channels supported in this module
7953 UCHAR ucChannelWidth; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
7954 UCHAR ucDensity; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
7955 UCHAR ucBankCol; // bit[3:2]= BANK ( =2:16bank, =1:8bank, =0:4bank ) bit[1:0]=Col ( =2: 10 bit, =1:9bit, =0:8bit )
7956 UCHAR ucMisc; // RANK_OF_THISMEMORY etc.
7957 UCHAR ucVREFI; // Not used.
7960 UCHAR ucMcTunningSetId; // MC phy registers set per.
7961 UCHAR ucRowNum;
7965 UCHAR ucMemoryVenderID; // [7:4] Revision, [3:0] Vendor code
7966 UCHAR ucRefreshRateFactor; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
7967 UCHAR ucFIFODepth; // FIFO depth can be detected during vendor detection, here is hardcoded per memory
7968 UCHAR ucCDR_Bandwidth; // [0:3]=Read CDR bandwidth, [4:7] - Write CDR Bandwidth
7980 UCHAR ucNumOfVRAMModule;
7990 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
7991 UCHAR ucNumOfVRAMModule;
8005 UCHAR ucMemDQ7_0ByteRemap; // DQ line byte remap, =0: Memory Data line BYTE0, =1: BYTE1, =2: BYTE2, =3: BYTE3
8007 UCHAR ucReservde[4];
8008 UCHAR ucNumOfVRAMModule;
8020 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8021 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8022 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8023 UCHAR ucReserved;
8036 UCHAR ucNumOfVRAMModule; // indicate number of VRAM module
8037 UCHAR ucMemoryClkPatchTblVer; // version of memory AC timing register list
8038 UCHAR ucVramModuleVer; // indicate ATOM_VRAM_MODUE version
8039 UCHAR ucMcPhyTileNum; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
8046 UCHAR ucByteRemapCh0;
8047 UCHAR ucByteRemapCh1;
8061 UCHAR aVID_PinsShift[9]; // 8 bit strap maximum+terminator
8068 UCHAR ucTrainingLoop;
8069 UCHAR ucReserved[3];
8087 UCHAR ucControl;
8088 UCHAR ucData;
8089 UCHAR ucSatus;
8090 UCHAR ucTemp;
8098 UCHAR ucAct;
8099 UCHAR ucData;
8145 UCHAR VbeSignature[4];
8148 UCHAR Capabilities[4];
8172 UCHAR Reserved[222];
8173 UCHAR OemData[256];
8181 UCHAR RedBPP;
8182 UCHAR GreenBPP;
8183 UCHAR BlueBPP;
8184 UCHAR ReservedBPP;
8187 UCHAR Reserved[14];
8194 UCHAR WinAAttributes; // db ? ; window A attributes
8195 UCHAR WinBAttributes; // db ? ; window B attributes
8206 UCHAR XCharSize; // db ? ; character cell width in pixels
8207 UCHAR YCharSize; // db ? ; character cell height in pixels
8208 UCHAR NumberOfPlanes; // db ? ; number of memory planes
8209 UCHAR BitsPerPixel; // db ? ; bits per pixel
8210 UCHAR NumberOfBanks; // db ? ; number of banks
8211 UCHAR MemoryModel; // db ? ; memory model type
8212 UCHAR BankSize; // db ? ; bank size in KB
8213 UCHAR NumberOfImagePages;// db ? ; number of images
8214 UCHAR ReservedForPageFunction;//db 1 ; reserved for page function
8217 UCHAR RedMaskSize; // db ? ; size of direct color red mask in bits
8218 UCHAR RedFieldPosition; // db ? ; bit position of lsb of red mask
8219 UCHAR GreenMaskSize; // db ? ; size of direct color green mask in bits
8220 UCHAR GreenFieldPosition; // db ? ; bit position of lsb of green mask
8221 UCHAR BlueMaskSize; // db ? ; size of direct color blue mask in bits
8222 UCHAR BlueFieldPosition; // db ? ; bit position of lsb of blue mask
8223 UCHAR RsvdMaskSize; // db ? ; size of direct color reserved mask in bits
8224 UCHAR RsvdFieldPosition; // db ? ; bit position of lsb of reserved mask
8225 UCHAR DirectColorModeInfo;// db ? ; direct color mode attributes
8234 UCHAR BnkNumberOfImagePages;// db ? ; number of images for banked modes
8235 UCHAR LinNumberOfImagPages; // db ? ; number of images for linear modes
8236 UCHAR LinRedMaskSize; // db ? ; size of direct color red mask(linear modes)
8237 UCHAR LinRedFieldPosition; // db ? ; bit position of lsb of red mask(linear modes)
8238 UCHAR LinGreenMaskSize; // db ? ; size of direct color green mask(linear modes)
8239 UCHAR LinGreenFieldPosition;// db ? ; bit position of lsb of green mask(linear modes)
8240 UCHAR LinBlueMaskSize; // db ? ; size of direct color blue mask(linear modes)
8241 UCHAR LinBlueFieldPosition; // db ? ; bit position of lsb of blue mask(linear modes)
8242 UCHAR LinRsvdMaskSize; // db ? ; size of direct color reserved mask(linear modes)
8243 UCHAR LinRsvdFieldPosition; // db ? ; bit position of lsb of reserved mask(linear modes)
8245 UCHAR Reserved; // db 190 dup (0)
8301 UCHAR ucTransmitterCmdTblId;
8302 UCHAR ucConfig;
8303 UCHAR ucEncoderID; //available 1st encoder ( default )
8304 UCHAR ucOptionEncoderID; //available 2nd encoder ( optional )
8305 UCHAR uc2ndEncoderID;
8306 UCHAR ucReserved;
8321 UCHAR ucEncoderID;
8322 UCHAR ucEncoderConfig;
8348 UCHAR ucPpllId;
8349 UCHAR ucPpllAttribute;
8362 UCHAR ucTransmitterCmdTblId;
8363 UCHAR ucConfig;
8364 UCHAR ucEncoderID; // available 1st encoder ( default )
8365 UCHAR ucOptionEncoderID; // available 2nd encoder ( optional )
8366 UCHAR uc2ndEncoderID;
8367 UCHAR ucReserved;
8377 UCHAR ucDCERevision;
8378 UCHAR ucMaxDispEngineNum;
8379 UCHAR ucMaxActiveDispEngineNum;
8380 UCHAR ucMaxPPLLNum;
8381 UCHAR ucCoreRefClkSource; // value of CORE_REF_CLK_SOURCE
8382 UCHAR ucDispCaps;
8383 UCHAR ucReserved[2];
8409 UCHAR ucChannelID;
8412 UCHAR ucReplyStatus;
8413 UCHAR ucDelay;
8415 UCHAR ucDataOutLen;
8416 UCHAR ucReserved;
8424 UCHAR ucChannelID;
8427 UCHAR ucReplyStatus;
8428 UCHAR ucDelay;
8430 UCHAR ucDataOutLen;
8431 UCHAR ucHPD_ID; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
8443 UCHAR ucConfig; // for DP training command
8444 UCHAR ucI2cId; // use for GET_SINK_TYPE command
8446 UCHAR ucAction;
8447 UCHAR ucStatus;
8448 UCHAR ucLaneNum;
8449 UCHAR ucReserved[2];
8461 UCHAR ucAuxId;
8462 UCHAR ucAction;
8463 UCHAR ucSinkType; // Iput and Output parameters.
8464 UCHAR ucHPDId; // Input parameter, used when ucAction = DP_SERVICE_V2_ACTION_DET_EXT_CONNECTION
8465 UCHAR ucReserved[2];
8497 UCHAR ucI2CSpeed;
8500 UCHAR ucRegIndex;
8501 UCHAR ucStatus;
8504 UCHAR ucFlag;
8505 UCHAR ucTransBytes;
8506 UCHAR ucSlaveAddr;
8507 UCHAR ucLineNumber;
8522 UCHAR ucCmd; // Input: To tell which action to take
8523 UCHAR ucReserved[3];
8529 UCHAR ucReturnCode; // Output: Return value base on action was taken
8530 UCHAR ucReserved[3];
8552 UCHAR ucHWBlkInst; // HW block instance, 0, 1, 2, ...
8553 UCHAR ucReserved[3];
8612 UCHAR ucStartBit;
8613 UCHAR ucEndBit;
8618 UCHAR ucEncodeMode;
8619 UCHAR ucPhySel;
8635 UCHAR ucCondition2;
8652 UCHAR ucEncodeMode;
8653 UCHAR ucPhySel;
8659 UCHAR ucEncodeMode;
8660 UCHAR ucPhySel;
8667 UCHAR ucGfxBlkId; //GFX blk id to be harvested, like CU, RB or PRIM
8668 UCHAR ucReserved; //reserved
8669 UCHAR ucActiveUnitNumPerSH; //requested active CU/RB/PRIM number per shader array
8670 UCHAR ucMaxUnitNumPerSH; //max CU/RB/PRIM number per shader array
8680 UCHAR PciRomSignature[2];
8681 UCHAR ucPciRomSizeIn512bytes;
8682 UCHAR ucJumpCoreMainInitBIOS;
8684 UCHAR PciReservedSpace[18];
8686 UCHAR Rsvd1d_1a[4];
8688 UCHAR CheckSum[14];
8689 UCHAR ucBiosMsgNumber;
8693 UCHAR ucSpeicalPostImageSizeIn512Bytes;
8694 UCHAR Rsved47_45[3];
8696 UCHAR Rsved4f_4a[6];
8698 UCHAR ucJumpCoreXFuncFarHandler;
8700 UCHAR ucRsved67;
8701 UCHAR ucJumpCoreVFuncFarHandler;
8703 UCHAR Rsved6d_6b[3];
8747 UCHAR ucDAC1_BG_Adjustment;
8748 UCHAR ucDAC1_DAC_Adjustment;
8751 UCHAR ucDAC2_CRT2_BG_Adjustment;
8752 UCHAR ucDAC2_CRT2_DAC_Adjustment;
8755 UCHAR ucDAC2_CRT2_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8756 UCHAR ucDAC2_NTSC_BG_Adjustment;
8757 UCHAR ucDAC2_NTSC_DAC_Adjustment;
8760 UCHAR ucDAC2_TV1_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8761 UCHAR ucDAC2_CV_BG_Adjustment;
8762 UCHAR ucDAC2_CV_DAC_Adjustment;
8765 UCHAR ucDAC2_CV_MUX_RegisterInfo; //Bit[4:0]=Bit position,Bit[7]=1:Active High;=0 Active Low
8766 UCHAR ucDAC2_PAL_BG_Adjustment;
8767 UCHAR ucDAC2_PAL_DAC_Adjustment;
8798 UCHAR bfConnectorType:4;
8799 UCHAR bfAssociatedDAC:4;
8801 UCHAR bfAssociatedDAC:4;
8802 UCHAR bfConnectorType:4;
8809 UCHAR ucAccess;
8830 UCHAR ucIntSrcBitmap;
8856 UCHAR ucPLL_ChargePump; // PLL charge-pump gain control
8857 UCHAR ucPLL_DutyCycle; // PLL duty cycle control
8858 UCHAR ucPLL_VCO_Gain; // PLL VCO gain control
8859 UCHAR ucPLL_VoltageSwing; // PLL driver voltage swing control
8875 UCHAR ucTVStandard; //Same as TV standards defined above,
8876 UCHAR ucPadding[1];
8881 UCHAR ucAttribute; //Same as other digital encoder attributes defined above
8882 UCHAR ucPadding[1];
8896 UCHAR ucDeviceType; //Use ATOM_DEVICE_xxx1_Index to indicate device type only.
8897 UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
8921 UCHAR ucXtransimitterID;
8922 UCHAR ucSupportedLink; // Bit field, bit0=1, single link supported;bit1=1,dual link supported
8923 UCHAR ucSequnceAlterID; // Even with the same external TMDS asic, it's possible that the program seqence alters
8925 UCHAR ucMasterAddress; // Address to control Master xTMDS Chip
8926 UCHAR ucSlaveAddress; // Address to control Slave xTMDS Chip
8931 UCHAR ucEnable; // ATOM_ENABLE=On or ATOM_DISABLE=Off
8932 UCHAR ucDevice; // ATOM_DEVICE_DFP1_INDEX....
8933 UCHAR ucPadding[2];
9001 UCHAR ucVoltageDropIndex; // index to GPIO table
9002 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9003 UCHAR ucMinTemperature;
9004 UCHAR ucMaxTemperature;
9005 UCHAR ucNumPciELanes; // number of PCIE lanes
9016 UCHAR ucVoltageDropIndex; // index to GPIO table
9017 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9018 UCHAR ucMinTemperature;
9019 UCHAR ucMaxTemperature;
9020 UCHAR ucNumPciELanes; // number of PCIE lanes
9031 UCHAR ucVoltageDropIndex; // index to Core (VDDC) votage table
9032 UCHAR ucSelectedPanel_RefreshRate;// panel refresh rate
9033 UCHAR ucMinTemperature;
9034 UCHAR ucMaxTemperature;
9035 UCHAR ucNumPciELanes; // number of PCIE lanes
9036 UCHAR ucVDDCI_VoltageDropIndex; // index to VDDCI votage table
9057 UCHAR ucOverdriveThermalController;
9058 UCHAR ucOverdriveI2cLine;
9059 UCHAR ucOverdriveIntBitmap;
9060 UCHAR ucOverdriveControllerAddress;
9061 UCHAR ucSizeOfPowerModeEntry;
9062 UCHAR ucNumOfPowerModeEntries;
9069 UCHAR ucOverdriveThermalController;
9070 UCHAR ucOverdriveI2cLine;
9071 UCHAR ucOverdriveIntBitmap;
9072 UCHAR ucOverdriveControllerAddress;
9073 UCHAR ucSizeOfPowerModeEntry;
9074 UCHAR ucNumOfPowerModeEntries;
9081 UCHAR ucOverdriveThermalController;
9082 UCHAR ucOverdriveI2cLine;
9083 UCHAR ucOverdriveIntBitmap;
9084 UCHAR ucOverdriveControllerAddress;
9085 UCHAR ucSizeOfPowerModeEntry;
9086 UCHAR ucNumOfPowerModeEntries;
9221 UCHAR ucRevision; // Holes set revision
9222 UCHAR ucAlgorithm; // Hash algorithm
9223 UCHAR ucSignatureType; // Signature type ( 0 - no signature, 1 - test, 2 - production )
9224 UCHAR ucReserved;
9234 UCHAR ucholesNo; // number of holes that follow
9250 UCHAR Revision;
9251 UCHAR Checksum;
9252 UCHAR OemId[6];
9253 UCHAR OemTableId[8]; //UINT64 OemTableId;
9274 UCHAR TableUUID[16]; //0x24
9295 UCHAR VbiosContent[];
9300 UCHAR Lib1Content[1];