Lines Matching refs:data
657 /* set index to data for continous read */
1108 u32 data, orig;
1110 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1111 data |= PCIE_LC_CNTL__LC_L0S_INACTIVITY_DEFAULT <<
1113 data |= PCIE_LC_CNTL__LC_L1_INACTIVITY_DEFAULT <<
1115 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1116 data |= PCIE_LC_CNTL__LC_DELAY_L1_EXIT_MASK;
1117 if (orig != data)
1118 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1123 u32 data, data1, orig;
1134 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1135 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
1136 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1137 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1138 if (orig != data)
1139 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1141 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1142 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1143 data |= 0x0024 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT;
1144 data |= PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_OVERRIDE_EN_MASK;
1145 if (orig != data)
1146 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1148 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1149 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1150 if (orig != data)
1151 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1153 orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1154 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1155 if (orig != data)
1156 WREG32_PCIE(ixPCIE_P_CNTL, data);
1158 data = RREG32_PCIE(ixPCIE_LC_L1_PM_SUBSTATE);
1160 if (data & PCIE_LC_L1_PM_SUBSTATE__LC_L1_SUBSTATES_OVERRIDE_EN_MASK &&
1161 (data & (PCIE_LC_L1_PM_SUBSTATE__LC_PCI_PM_L1_2_OVERRIDE_MASK |
1173 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL6);
1174 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK;
1175 if (orig != data)
1176 WREG32_PCIE(ixPCIE_LC_CNTL6, data);
1178 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1179 data |= PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1180 if (orig != data)
1181 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1183 pci_read_config_dword(adev->pdev, LINK_CAP, &data);
1184 if (!(data & PCIE_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK))
1188 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1189 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK | THM_CLK_CNTL__TMON_CLK_SEL_MASK);
1190 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1192 if (orig != data)
1193 WREG32_SMC(ixTHM_CLK_CNTL, data);
1195 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1196 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1198 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1200 data |= (0x20 << MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT);
1201 if (orig != data)
1202 WREG32_SMC(ixMISC_CLK_CTRL, data);
1204 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1205 data |= CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK;
1206 if (orig != data)
1207 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1209 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1210 data |= CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK;
1211 if (orig != data)
1212 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1214 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1215 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1216 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1217 if (orig != data)
1218 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1220 orig = data = RREG32_PCIE(ixCPM_CONTROL);
1221 data |= (CPM_CONTROL__REFCLK_XSTCLK_ENABLE_MASK |
1223 if (orig != data)
1224 WREG32_PCIE(ixCPM_CONTROL, data);
1226 orig = data = RREG32_PCIE(ixPCIE_CONFIG_CNTL);
1227 data &= ~PCIE_CONFIG_CNTL__DYN_CLK_LATENCY_MASK;
1228 data |= (0xE << PCIE_CONFIG_CNTL__DYN_CLK_LATENCY__SHIFT);
1229 if (orig != data)
1230 WREG32_PCIE(ixPCIE_CONFIG_CNTL, data);
1232 orig = data = RREG32(mmBIF_CLK_CTRL);
1233 data |= BIF_CLK_CTRL__BIF_XSTCLK_READY_MASK;
1234 if (orig != data)
1235 WREG32(mmBIF_CLK_CTRL, data);
1237 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL7);
1238 data |= PCIE_LC_CNTL7__LC_L1_SIDEBAND_CLKREQ_PDWN_EN_MASK;
1239 if (orig != data)
1240 WREG32_PCIE(ixPCIE_LC_CNTL7, data);
1242 orig = data = RREG32_PCIE(ixPCIE_HW_DEBUG);
1243 data |= PCIE_HW_DEBUG__HW_01_DEBUG_MASK;
1244 if (orig != data)
1245 WREG32_PCIE(ixPCIE_HW_DEBUG, data);
1247 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1248 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
1249 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1251 data &= ~PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK;
1252 if (orig != data)
1253 WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1259 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1261 if (((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) == PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) &&
1264 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1265 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1266 if (orig != data)
1267 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1273 orig = data = RREG32_PCIE(ixPCIE_LC_TRAINING_CNTL);
1274 data &= ~PCIE_LC_TRAINING_CNTL__LC_DISABLE_TRAINING_BIT_ARCH_MASK;
1275 if (orig != data)
1276 WREG32_PCIE(ixPCIE_LC_TRAINING_CNTL, data);
1767 uint32_t temp, data;
1769 temp = data = RREG32_PCIE(ixPCIE_CNTL2);
1772 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1776 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1780 if (temp != data)
1781 WREG32_PCIE(ixPCIE_CNTL2, data);
1787 uint32_t temp, data;
1789 temp = data = RREG32(mmHDP_HOST_PATH_CNTL);
1792 data &= ~HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1794 data |= HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK;
1796 if (temp != data)
1797 WREG32(mmHDP_HOST_PATH_CNTL, data);
1803 uint32_t temp, data;
1805 temp = data = RREG32(mmHDP_MEM_POWER_LS);
1808 data |= HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1810 data &= ~HDP_MEM_POWER_LS__LS_ENABLE_MASK;
1812 if (temp != data)
1813 WREG32(mmHDP_MEM_POWER_LS, data);
1819 uint32_t temp, data;
1821 temp = data = RREG32(0x157a);
1824 data |= 1;
1826 data &= ~1;
1828 if (temp != data)
1829 WREG32(0x157a, data);
1836 uint32_t temp, data;
1838 temp = data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
1841 data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1844 data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
1847 if (temp != data)
1848 WREG32_SMC(ixCGTT_ROM_CLK_CTRL0, data);
2020 int data;
2026 data = RREG32_PCIE(ixPCIE_CNTL2);
2027 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
2031 data = RREG32(mmHDP_MEM_POWER_LS);
2032 if (data & HDP_MEM_POWER_LS__LS_ENABLE_MASK)
2036 data = RREG32(mmHDP_HOST_PATH_CNTL);
2037 if (!(data & HDP_HOST_PATH_CNTL__CLOCK_GATING_DIS_MASK))
2041 data = RREG32_SMC(ixCGTT_ROM_CLK_CTRL0);
2042 if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))