Lines Matching defs:adev
257 static int vi_query_video_codecs(struct amdgpu_device *adev, bool encode,
260 switch (adev->asic_type) {
298 static u32 vi_pcie_rreg(struct amdgpu_device *adev, u32 reg)
303 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
307 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
311 static void vi_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
315 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
320 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
323 static u32 vi_smc_rreg(struct amdgpu_device *adev, u32 reg)
328 spin_lock_irqsave(&adev->smc_idx_lock, flags);
331 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
335 static void vi_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
339 spin_lock_irqsave(&adev->smc_idx_lock, flags);
342 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
349 static u32 cz_smc_rreg(struct amdgpu_device *adev, u32 reg)
354 spin_lock_irqsave(&adev->smc_idx_lock, flags);
357 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
361 static void cz_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
365 spin_lock_irqsave(&adev->smc_idx_lock, flags);
368 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
371 static u32 vi_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
376 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
379 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
383 static void vi_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
387 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
390 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
393 static u32 vi_didt_rreg(struct amdgpu_device *adev, u32 reg)
398 spin_lock_irqsave(&adev->didt_idx_lock, flags);
401 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
405 static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
409 spin_lock_irqsave(&adev->didt_idx_lock, flags);
412 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
415 static u32 vi_gc_cac_rreg(struct amdgpu_device *adev, u32 reg)
420 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
423 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
427 static void vi_gc_cac_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
431 spin_lock_irqsave(&adev->gc_cac_idx_lock, flags);
434 spin_unlock_irqrestore(&adev->gc_cac_idx_lock, flags);
485 static void vi_init_golden_registers(struct amdgpu_device *adev)
488 mutex_lock(&adev->grbm_idx_mutex);
490 if (amdgpu_sriov_vf(adev)) {
491 xgpu_vi_init_golden_registers(adev);
492 mutex_unlock(&adev->grbm_idx_mutex);
496 switch (adev->asic_type) {
498 amdgpu_device_program_register_sequence(adev,
503 amdgpu_device_program_register_sequence(adev,
508 amdgpu_device_program_register_sequence(adev,
513 amdgpu_device_program_register_sequence(adev,
518 amdgpu_device_program_register_sequence(adev,
529 mutex_unlock(&adev->grbm_idx_mutex);
535 * @adev: amdgpu_device pointer
540 static u32 vi_get_xclk(struct amdgpu_device *adev)
542 u32 reference_clock = adev->clock.spll.reference_freq;
545 if (adev->flags & AMD_IS_APU) {
546 switch (adev->asic_type) {
569 * @adev: amdgpu_device pointer
579 void vi_srbm_select(struct amdgpu_device *adev,
590 static bool vi_read_disabled_bios(struct amdgpu_device *adev)
600 if (adev->mode_info.num_crtc) {
609 if (adev->mode_info.num_crtc) {
622 r = amdgpu_read_bios(adev);
626 if (adev->mode_info.num_crtc) {
635 static bool vi_read_bios_from_rom(struct amdgpu_device *adev,
647 if (adev->flags & AMD_IS_APU)
653 spin_lock_irqsave(&adev->smc_idx_lock, flags);
661 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
745 static uint32_t vi_get_register_value(struct amdgpu_device *adev,
756 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
758 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
760 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
762 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
765 mutex_lock(&adev->grbm_idx_mutex);
767 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
772 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
773 mutex_unlock(&adev->grbm_idx_mutex);
780 return adev->gfx.config.gb_addr_config;
782 return adev->gfx.config.mc_arb_ramcfg;
816 return adev->gfx.config.tile_mode_array[idx];
834 return adev->gfx.config.macrotile_mode_array[idx];
841 static int vi_read_register(struct amdgpu_device *adev, u32 se_num,
853 *value = vi_get_register_value(adev, indexed, se_num, sh_num,
863 * @adev: amdgpu_device pointer
869 static int vi_asic_pci_config_reset(struct amdgpu_device *adev)
874 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
877 pci_clear_master(adev->pdev);
879 amdgpu_device_pci_config_reset(adev);
884 for (i = 0; i < adev->usec_timeout; i++) {
887 pci_set_master(adev->pdev);
888 adev->has_hw_reset = true;
895 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
900 static bool vi_asic_supports_baco(struct amdgpu_device *adev)
902 switch (adev->asic_type) {
909 return amdgpu_dpm_is_baco_supported(adev);
916 vi_asic_reset_method(struct amdgpu_device *adev)
925 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
928 switch (adev->asic_type) {
935 baco_reset = amdgpu_dpm_is_baco_supported(adev);
951 * @adev: amdgpu_device pointer
957 static int vi_asic_reset(struct amdgpu_device *adev)
962 if (adev->flags & AMD_IS_APU)
965 if (vi_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
966 dev_info(adev->dev, "BACO reset\n");
967 r = amdgpu_dpm_baco_reset(adev);
969 dev_info(adev->dev, "PCI CONFIG reset\n");
970 r = vi_asic_pci_config_reset(adev);
976 static u32 vi_get_config_memsize(struct amdgpu_device *adev)
981 static int vi_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
988 r = amdgpu_atombios_get_clock_dividers(adev,
996 if (adev->flags & AMD_IS_APU)
1006 if (adev->flags & AMD_IS_APU) {
1027 static int vi_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1031 if (adev->flags & AMD_IS_APU) {
1032 r = vi_set_uvd_clock(adev, vclk, ixGNB_CLK2_DFS_CNTL, ixGNB_CLK2_STATUS);
1036 r = vi_set_uvd_clock(adev, dclk, ixGNB_CLK1_DFS_CNTL, ixGNB_CLK1_STATUS);
1040 r = vi_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1044 r = vi_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1052 static int vi_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1062 if (adev->flags & AMD_IS_APU) {
1074 r = amdgpu_atombios_get_clock_dividers(adev,
1106 static void vi_enable_aspm(struct amdgpu_device *adev)
1121 static void vi_program_aspm(struct amdgpu_device *adev)
1127 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_pcie_dynamic_switching_supported())
1130 if (adev->flags & AMD_IS_APU ||
1131 adev->asic_type < CHIP_POLARIS10)
1159 pci_read_config_dword(adev->pdev, PCIE_L1_PM_SUB_CNTL, &data1);
1183 pci_read_config_dword(adev->pdev, LINK_CAP, &data);
1257 vi_enable_aspm(adev);
1270 if ((adev->asic_type == CHIP_POLARIS12 &&
1271 !(ASICID_IS_P23(adev->pdev->device, adev->pdev->revision))) ||
1272 ASIC_IS_P22(adev->asic_type, adev->external_rev_id)) {
1280 static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
1286 if (adev->flags & AMD_IS_APU)
1302 static uint32_t vi_get_rev_id(struct amdgpu_device *adev)
1304 if (adev->flags & AMD_IS_APU)
1312 static void vi_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1322 static void vi_invalidate_hdp(struct amdgpu_device *adev,
1333 static bool vi_need_full_reset(struct amdgpu_device *adev)
1335 switch (adev->asic_type) {
1354 static void vi_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1364 if (adev->flags & AMD_IS_APU)
1400 static uint64_t vi_get_pcie_replay_count(struct amdgpu_device *adev)
1412 static bool vi_need_reset_on_init(struct amdgpu_device *adev)
1416 if (adev->flags & AMD_IS_APU)
1429 static void vi_pre_asic_init(struct amdgpu_device *adev)
1461 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1463 if (adev->flags & AMD_IS_APU) {
1464 adev->smc_rreg = &cz_smc_rreg;
1465 adev->smc_wreg = &cz_smc_wreg;
1467 adev->smc_rreg = &vi_smc_rreg;
1468 adev->smc_wreg = &vi_smc_wreg;
1470 adev->pcie_rreg = &vi_pcie_rreg;
1471 adev->pcie_wreg = &vi_pcie_wreg;
1472 adev->uvd_ctx_rreg = &vi_uvd_ctx_rreg;
1473 adev->uvd_ctx_wreg = &vi_uvd_ctx_wreg;
1474 adev->didt_rreg = &vi_didt_rreg;
1475 adev->didt_wreg = &vi_didt_wreg;
1476 adev->gc_cac_rreg = &vi_gc_cac_rreg;
1477 adev->gc_cac_wreg = &vi_gc_cac_wreg;
1479 adev->asic_funcs = &vi_asic_funcs;
1481 adev->rev_id = vi_get_rev_id(adev);
1482 adev->external_rev_id = 0xFF;
1483 switch (adev->asic_type) {
1485 adev->cg_flags = 0;
1486 adev->pg_flags = 0;
1487 adev->external_rev_id = 0x1;
1490 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1507 adev->pg_flags = 0;
1508 adev->external_rev_id = adev->rev_id + 0x3c;
1511 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1524 adev->pg_flags = 0;
1525 adev->external_rev_id = adev->rev_id + 0x14;
1528 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1547 adev->pg_flags = 0;
1548 adev->external_rev_id = adev->rev_id + 0x5A;
1551 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1570 adev->pg_flags = 0;
1571 adev->external_rev_id = adev->rev_id + 0x50;
1574 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
1593 adev->pg_flags = 0;
1594 adev->external_rev_id = adev->rev_id + 0x64;
1597 adev->cg_flags = 0;
1617 adev->pg_flags = 0;
1618 adev->external_rev_id = adev->rev_id + 0x6E;
1621 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1637 adev->pg_flags = 0;
1638 if (adev->rev_id != 0x00 || CZ_REV_BRISTOL(adev->pdev->revision)) {
1639 adev->pg_flags |= AMD_PG_SUPPORT_GFX_SMG |
1645 adev->external_rev_id = adev->rev_id + 0x1;
1648 adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
1662 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
1668 adev->external_rev_id = adev->rev_id + 0x61;
1675 if (amdgpu_sriov_vf(adev)) {
1676 amdgpu_virt_init_setting(adev);
1677 xgpu_vi_mailbox_set_irq_funcs(adev);
1685 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1687 if (amdgpu_sriov_vf(adev))
1688 xgpu_vi_mailbox_get_irq(adev);
1695 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1697 if (amdgpu_sriov_vf(adev))
1698 xgpu_vi_mailbox_add_irq_id(adev);
1710 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1713 vi_init_golden_registers(adev);
1715 vi_program_aspm(adev);
1717 vi_enable_doorbell_aperture(adev, true);
1724 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1727 vi_enable_doorbell_aperture(adev, false);
1729 if (amdgpu_sriov_vf(adev))
1730 xgpu_vi_mailbox_put_irq(adev);
1737 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1739 return vi_common_hw_fini(adev);
1744 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1746 return vi_common_hw_init(adev);
1764 static void vi_update_bif_medium_grain_light_sleep(struct amdgpu_device *adev,
1771 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS))
1784 static void vi_update_hdp_medium_grain_clock_gating(struct amdgpu_device *adev,
1791 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
1800 static void vi_update_hdp_light_sleep(struct amdgpu_device *adev,
1807 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
1816 static void vi_update_drm_light_sleep(struct amdgpu_device *adev,
1823 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS))
1833 static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
1840 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
1856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1858 if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
1859 if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
1863 if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
1873 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1876 if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
1877 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
1881 if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
1891 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1894 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
1895 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
1899 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
1909 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1913 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
1923 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1925 if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
1935 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1938 if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
1949 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1952 if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
1963 amdgpu_dpm_set_clockgating_by_smu(adev, msg_id);
1971 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1973 if (amdgpu_sriov_vf(adev))
1976 switch (adev->asic_type) {
1978 vi_update_bif_medium_grain_light_sleep(adev,
1980 vi_update_hdp_medium_grain_clock_gating(adev,
1982 vi_update_hdp_light_sleep(adev,
1984 vi_update_rom_medium_grain_clock_gating(adev,
1989 vi_update_bif_medium_grain_light_sleep(adev,
1991 vi_update_hdp_medium_grain_clock_gating(adev,
1993 vi_update_hdp_light_sleep(adev,
1995 vi_update_drm_light_sleep(adev,
2003 vi_common_set_clockgating_state_by_smu(adev, state);
2019 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2022 if (amdgpu_sriov_vf(adev))
2073 void vi_set_virt_ops(struct amdgpu_device *adev)
2075 adev->virt.ops = &xgpu_vi_virt_ops;
2078 int vi_set_ip_blocks(struct amdgpu_device *adev)
2080 amdgpu_device_set_sriov_virtual_display(adev);
2082 switch (adev->asic_type) {
2085 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2086 amdgpu_device_ip_block_add(adev, &gmc_v7_4_ip_block);
2087 amdgpu_device_ip_block_add(adev, &iceland_ih_ip_block);
2088 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2089 amdgpu_device_ip_block_add(adev, &sdma_v2_4_ip_block);
2090 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2091 if (adev->enable_virtual_display)
2092 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2095 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2096 amdgpu_device_ip_block_add(adev, &gmc_v8_5_ip_block);
2097 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2098 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2099 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2100 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2101 if (adev->enable_virtual_display)
2102 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2104 else if (amdgpu_device_has_dc_support(adev))
2105 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2108 amdgpu_device_ip_block_add(adev, &dce_v10_1_ip_block);
2109 if (!amdgpu_sriov_vf(adev)) {
2110 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2111 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2115 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2116 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2117 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2118 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2119 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2120 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2121 if (adev->enable_virtual_display)
2122 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2124 else if (amdgpu_device_has_dc_support(adev))
2125 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2128 amdgpu_device_ip_block_add(adev, &dce_v10_0_ip_block);
2129 if (!amdgpu_sriov_vf(adev)) {
2130 amdgpu_device_ip_block_add(adev, &uvd_v5_0_ip_block);
2131 amdgpu_device_ip_block_add(adev, &vce_v3_0_ip_block);
2138 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2139 amdgpu_device_ip_block_add(adev, &gmc_v8_1_ip_block);
2140 amdgpu_device_ip_block_add(adev, &tonga_ih_ip_block);
2141 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2142 amdgpu_device_ip_block_add(adev, &sdma_v3_1_ip_block);
2143 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2144 if (adev->enable_virtual_display)
2145 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2147 else if (amdgpu_device_has_dc_support(adev))
2148 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2151 amdgpu_device_ip_block_add(adev, &dce_v11_2_ip_block);
2152 amdgpu_device_ip_block_add(adev, &uvd_v6_3_ip_block);
2153 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2156 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2157 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2158 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2159 amdgpu_device_ip_block_add(adev, &gfx_v8_0_ip_block);
2160 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2161 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2162 if (adev->enable_virtual_display)
2163 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2165 else if (amdgpu_device_has_dc_support(adev))
2166 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2169 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2170 amdgpu_device_ip_block_add(adev, &uvd_v6_0_ip_block);
2171 amdgpu_device_ip_block_add(adev, &vce_v3_1_ip_block);
2173 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2177 amdgpu_device_ip_block_add(adev, &vi_common_ip_block);
2178 amdgpu_device_ip_block_add(adev, &gmc_v8_0_ip_block);
2179 amdgpu_device_ip_block_add(adev, &cz_ih_ip_block);
2180 amdgpu_device_ip_block_add(adev, &gfx_v8_1_ip_block);
2181 amdgpu_device_ip_block_add(adev, &sdma_v3_0_ip_block);
2182 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2183 if (adev->enable_virtual_display)
2184 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2186 else if (amdgpu_device_has_dc_support(adev))
2187 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2190 amdgpu_device_ip_block_add(adev, &dce_v11_0_ip_block);
2191 amdgpu_device_ip_block_add(adev, &uvd_v6_2_ip_block);
2192 amdgpu_device_ip_block_add(adev, &vce_v3_4_ip_block);
2194 amdgpu_device_ip_block_add(adev, &acp_ip_block);
2205 void legacy_doorbell_index_init(struct amdgpu_device *adev)
2207 adev->doorbell_index.kiq = AMDGPU_DOORBELL_KIQ;
2208 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL_MEC_RING0;
2209 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL_MEC_RING1;
2210 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL_MEC_RING2;
2211 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL_MEC_RING3;
2212 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL_MEC_RING4;
2213 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL_MEC_RING5;
2214 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL_MEC_RING6;
2215 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL_MEC_RING7;
2216 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL_GFX_RING0;
2217 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL_sDMA_ENGINE0;
2218 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL_sDMA_ENGINE1;
2219 adev->doorbell_index.ih = AMDGPU_DOORBELL_IH;
2220 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL_MAX_ASSIGNMENT;