Lines Matching refs:data
2436 u32 data, orig;
2445 orig = data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
2446 data &= ~LC_XMIT_N_FTS_MASK;
2447 data |= LC_XMIT_N_FTS(0x24) | LC_XMIT_N_FTS_OVERRIDE_EN;
2448 if (orig != data)
2449 WREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL, data);
2451 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL3);
2452 data |= LC_GO_TO_RECOVERY;
2453 if (orig != data)
2454 WREG32_PCIE_PORT(PCIE_LC_CNTL3, data);
2456 orig = data = RREG32_PCIE(PCIE_P_CNTL);
2457 data |= P_IGNORE_EDB_ERR;
2458 if (orig != data)
2459 WREG32_PCIE(PCIE_P_CNTL, data);
2461 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
2462 data &= ~(LC_L0S_INACTIVITY_MASK | LC_L1_INACTIVITY_MASK);
2463 data |= LC_PMI_TO_L1_DIS;
2465 data |= LC_L0S_INACTIVITY(7);
2468 data |= LC_L1_INACTIVITY(7);
2469 data &= ~LC_PMI_TO_L1_DIS;
2470 if (orig != data)
2471 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
2476 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2477 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
2478 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
2479 if (orig != data)
2480 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2482 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2483 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
2484 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
2485 if (orig != data)
2486 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2488 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2489 data &= ~(PLL_POWER_STATE_IN_OFF_0_MASK | PLL_POWER_STATE_IN_TXS2_0_MASK);
2490 data |= PLL_POWER_STATE_IN_OFF_0(7) | PLL_POWER_STATE_IN_TXS2_0(7);
2491 if (orig != data)
2492 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2494 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2495 data &= ~(PLL_POWER_STATE_IN_OFF_1_MASK | PLL_POWER_STATE_IN_TXS2_1_MASK);
2496 data |= PLL_POWER_STATE_IN_OFF_1(7) | PLL_POWER_STATE_IN_TXS2_1(7);
2497 if (orig != data)
2498 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2501 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2502 data &= ~PLL_RAMP_UP_TIME_0_MASK;
2503 if (orig != data)
2504 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2506 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2507 data &= ~PLL_RAMP_UP_TIME_1_MASK;
2508 if (orig != data)
2509 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2511 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
2512 data &= ~PLL_RAMP_UP_TIME_2_MASK;
2513 if (orig != data)
2514 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
2516 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
2517 data &= ~PLL_RAMP_UP_TIME_3_MASK;
2518 if (orig != data)
2519 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
2521 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2522 data &= ~PLL_RAMP_UP_TIME_0_MASK;
2523 if (orig != data)
2524 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2526 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2527 data &= ~PLL_RAMP_UP_TIME_1_MASK;
2528 if (orig != data)
2529 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2531 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
2532 data &= ~PLL_RAMP_UP_TIME_2_MASK;
2533 if (orig != data)
2534 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
2536 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
2537 data &= ~PLL_RAMP_UP_TIME_3_MASK;
2538 if (orig != data)
2539 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
2541 orig = data = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2542 data &= ~LC_DYN_LANES_PWR_STATE_MASK;
2543 data |= LC_DYN_LANES_PWR_STATE(3);
2544 if (orig != data)
2545 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, data);
2547 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
2548 data &= ~LS2_EXIT_TIME_MASK;
2550 data |= LS2_EXIT_TIME(5);
2551 if (orig != data)
2552 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
2554 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
2555 data &= ~LS2_EXIT_TIME_MASK;
2557 data |= LS2_EXIT_TIME(5);
2558 if (orig != data)
2559 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
2575 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL2);
2576 data |= LC_ALLOW_PDWN_IN_L1 | LC_ALLOW_PDWN_IN_L23;
2577 if (orig != data)
2578 WREG32_PCIE_PORT(PCIE_LC_CNTL2, data);
2580 orig = data = RREG32(THM_CLK_CNTL);
2581 data &= ~(CMON_CLK_SEL_MASK | TMON_CLK_SEL_MASK);
2582 data |= CMON_CLK_SEL(1) | TMON_CLK_SEL(1);
2583 if (orig != data)
2584 WREG32(THM_CLK_CNTL, data);
2586 orig = data = RREG32(MISC_CLK_CNTL);
2587 data &= ~(DEEP_SLEEP_CLK_SEL_MASK | ZCLK_SEL_MASK);
2588 data |= DEEP_SLEEP_CLK_SEL(1) | ZCLK_SEL(1);
2589 if (orig != data)
2590 WREG32(MISC_CLK_CNTL, data);
2592 orig = data = RREG32(CG_CLKPIN_CNTL);
2593 data &= ~BCLK_AS_XCLK;
2594 if (orig != data)
2595 WREG32(CG_CLKPIN_CNTL, data);
2597 orig = data = RREG32(CG_CLKPIN_CNTL_2);
2598 data &= ~FORCE_BIF_REFCLK_EN;
2599 if (orig != data)
2600 WREG32(CG_CLKPIN_CNTL_2, data);
2602 orig = data = RREG32(MPLL_BYPASSCLK_SEL);
2603 data &= ~MPLL_CLKOUT_SEL_MASK;
2604 data |= MPLL_CLKOUT_SEL(4);
2605 if (orig != data)
2606 WREG32(MPLL_BYPASSCLK_SEL, data);
2608 orig = data = RREG32(SPLL_CNTL_MODE);
2609 data &= ~SPLL_REFCLK_SEL_MASK;
2610 if (orig != data)
2611 WREG32(SPLL_CNTL_MODE, data);
2615 if (orig != data)
2616 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);
2619 orig = data = RREG32_PCIE(PCIE_CNTL2);
2620 data |= SLV_MEM_LS_EN | MST_MEM_LS_EN | REPLAY_MEM_LS_EN;
2621 if (orig != data)
2622 WREG32_PCIE(PCIE_CNTL2, data);
2625 data = RREG32_PCIE_PORT(PCIE_LC_N_FTS_CNTL);
2626 if((data & LC_N_FTS_MASK) == LC_N_FTS_MASK) {
2627 data = RREG32_PCIE(PCIE_LC_STATUS1);
2628 if ((data & LC_REVERSE_XMIT) && (data & LC_REVERSE_RCVR)) {
2629 orig = data = RREG32_PCIE_PORT(PCIE_LC_CNTL);
2630 data &= ~LC_L0S_INACTIVITY_MASK;
2631 if (orig != data)
2632 WREG32_PCIE_PORT(PCIE_LC_CNTL, data);