Lines Matching defs:adev
989 static int si_query_video_codecs(struct amdgpu_device *adev, bool encode,
992 switch (adev->asic_type) {
1018 static u32 si_pcie_rreg(struct amdgpu_device *adev, u32 reg)
1023 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1027 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1031 static void si_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1035 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1040 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1043 static u32 si_pciep_rreg(struct amdgpu_device *adev, u32 reg)
1048 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1052 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1056 static void si_pciep_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1060 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
1065 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
1068 static u32 si_smc_rreg(struct amdgpu_device *adev, u32 reg)
1073 spin_lock_irqsave(&adev->smc_idx_lock, flags);
1076 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
1080 static void si_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1084 spin_lock_irqsave(&adev->smc_idx_lock, flags);
1087 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
1090 static u32 si_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
1095 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
1098 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
1102 static void si_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
1106 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
1109 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
1164 static uint32_t si_get_register_value(struct amdgpu_device *adev,
1175 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1177 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1179 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1182 mutex_lock(&adev->grbm_idx_mutex);
1184 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
1189 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1190 mutex_unlock(&adev->grbm_idx_mutex);
1197 return adev->gfx.config.gb_addr_config;
1199 return adev->gfx.config.mc_arb_ramcfg;
1233 return adev->gfx.config.tile_mode_array[idx];
1239 static int si_read_register(struct amdgpu_device *adev, u32 se_num,
1251 *value = si_get_register_value(adev, indexed, se_num, sh_num,
1258 static bool si_read_disabled_bios(struct amdgpu_device *adev)
1268 if (adev->mode_info.num_crtc) {
1277 if (adev->mode_info.num_crtc) {
1290 r = amdgpu_read_bios(adev);
1294 if (adev->mode_info.num_crtc) {
1306 static bool si_read_bios_from_rom(struct amdgpu_device *adev,
1317 if (adev->flags & AMD_IS_APU)
1330 static void si_set_clk_bypass_mode(struct amdgpu_device *adev)
1342 for (i = 0; i < adev->usec_timeout; i++) {
1357 static void si_spll_powerdown(struct amdgpu_device *adev)
1378 static int si_gpu_pci_config_reset(struct amdgpu_device *adev)
1383 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1386 si_set_clk_bypass_mode(adev);
1388 si_spll_powerdown(adev);
1390 pci_clear_master(adev->pdev);
1392 amdgpu_device_pci_config_reset(adev);
1397 for (i = 0; i < adev->usec_timeout; i++) {
1400 pci_set_master(adev->pdev);
1401 adev->has_hw_reset = true;
1407 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1412 static bool si_asic_supports_baco(struct amdgpu_device *adev)
1418 si_asic_reset_method(struct amdgpu_device *adev)
1424 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
1430 static int si_asic_reset(struct amdgpu_device *adev)
1434 switch (si_asic_reset_method(adev)) {
1436 dev_info(adev->dev, "PCI reset\n");
1437 r = amdgpu_device_pci_reset(adev);
1440 dev_info(adev->dev, "PCI CONFIG reset\n");
1441 r = si_gpu_pci_config_reset(adev);
1448 static u32 si_get_config_memsize(struct amdgpu_device *adev)
1453 static void si_vga_set_state(struct amdgpu_device *adev, bool state)
1467 static u32 si_get_xclk(struct amdgpu_device *adev)
1469 u32 reference_clock = adev->clock.spll.reference_freq;
1483 static void si_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1493 static void si_invalidate_hdp(struct amdgpu_device *adev,
1504 static bool si_need_full_reset(struct amdgpu_device *adev)
1510 static bool si_need_reset_on_init(struct amdgpu_device *adev)
1515 static int si_get_pcie_lanes(struct amdgpu_device *adev)
1519 if (adev->flags & AMD_IS_APU)
1540 static void si_set_pcie_lanes(struct amdgpu_device *adev, int lanes)
1544 if (adev->flags & AMD_IS_APU)
1580 static void si_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1590 if (adev->flags & AMD_IS_APU)
1626 static uint64_t si_get_pcie_replay_count(struct amdgpu_device *adev)
1638 static int si_uvd_send_upll_ctlreq(struct amdgpu_device *adev,
1696 * @adev: amdgpu_device pointer
1713 static int si_calc_upll_dividers(struct amdgpu_device *adev,
1723 unsigned vco_freq, ref_freq = adev->clock.spll.reference_freq;
1775 static int si_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1793 r = si_calc_upll_dividers(adev, vclk, dclk, 125000, 250000,
1813 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
1852 r = si_uvd_send_upll_ctlreq(adev, CG_UPLL_FUNC_CNTL);
1866 static int si_vce_send_vcepll_ctlreq(struct amdgpu_device *adev)
1898 static int si_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1919 r = si_calc_upll_dividers(adev, evclk, ecclk, 125000, 250000,
1942 r = si_vce_send_vcepll_ctlreq(adev);
1976 r = si_vce_send_vcepll_ctlreq(adev);
1990 static void si_pre_asic_init(struct amdgpu_device *adev)
2019 static uint32_t si_get_rev_id(struct amdgpu_device *adev)
2027 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2029 adev->smc_rreg = &si_smc_rreg;
2030 adev->smc_wreg = &si_smc_wreg;
2031 adev->pcie_rreg = &si_pcie_rreg;
2032 adev->pcie_wreg = &si_pcie_wreg;
2033 adev->pciep_rreg = &si_pciep_rreg;
2034 adev->pciep_wreg = &si_pciep_wreg;
2035 adev->uvd_ctx_rreg = si_uvd_ctx_rreg;
2036 adev->uvd_ctx_wreg = si_uvd_ctx_wreg;
2037 adev->didt_rreg = NULL;
2038 adev->didt_wreg = NULL;
2040 adev->asic_funcs = &si_asic_funcs;
2042 adev->rev_id = si_get_rev_id(adev);
2043 adev->external_rev_id = 0xFF;
2044 switch (adev->asic_type) {
2046 adev->cg_flags =
2060 adev->pg_flags = 0;
2061 adev->external_rev_id = (adev->rev_id == 0) ? 1 :
2062 (adev->rev_id == 1) ? 5 : 6;
2065 adev->cg_flags =
2081 adev->pg_flags = 0;
2082 adev->external_rev_id = adev->rev_id + 20;
2086 adev->cg_flags =
2102 adev->pg_flags = 0;
2104 adev->external_rev_id = adev->rev_id + 40;
2107 adev->cg_flags =
2122 adev->pg_flags = 0;
2123 adev->external_rev_id = 60;
2126 adev->cg_flags =
2140 adev->pg_flags = 0;
2141 adev->external_rev_id = 70;
2162 static void si_init_golden_registers(struct amdgpu_device *adev)
2164 switch (adev->asic_type) {
2166 amdgpu_device_program_register_sequence(adev,
2169 amdgpu_device_program_register_sequence(adev,
2172 amdgpu_device_program_register_sequence(adev,
2175 amdgpu_device_program_register_sequence(adev,
2180 amdgpu_device_program_register_sequence(adev,
2183 amdgpu_device_program_register_sequence(adev,
2186 amdgpu_device_program_register_sequence(adev,
2191 amdgpu_device_program_register_sequence(adev,
2194 amdgpu_device_program_register_sequence(adev,
2197 amdgpu_device_program_register_sequence(adev,
2200 amdgpu_device_program_register_sequence(adev,
2205 amdgpu_device_program_register_sequence(adev,
2208 amdgpu_device_program_register_sequence(adev,
2211 amdgpu_device_program_register_sequence(adev,
2216 amdgpu_device_program_register_sequence(adev,
2219 amdgpu_device_program_register_sequence(adev,
2222 amdgpu_device_program_register_sequence(adev,
2233 static void si_pcie_gen3_enable(struct amdgpu_device *adev)
2235 struct pci_dev *root = adev->pdev->bus->self;
2240 if (pci_is_root_bus(adev->pdev->bus))
2246 if (adev->flags & AMD_IS_APU)
2249 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
2256 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
2262 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
2270 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
2273 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
2280 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
2297 pcie_capability_read_word(adev->pdev,
2305 pcie_capability_read_word(adev->pdev,
2311 pcie_capability_read_word(adev->pdev,
2329 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
2345 pcie_capability_read_word(adev->pdev,
2353 pcie_capability_write_word(adev->pdev,
2368 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
2371 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
2373 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
2377 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
2383 for (i = 0; i < adev->usec_timeout; i++) {
2391 static inline u32 si_pif_phy0_rreg(struct amdgpu_device *adev, u32 reg)
2396 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
2399 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
2403 static inline void si_pif_phy0_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
2407 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
2410 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
2413 static inline u32 si_pif_phy1_rreg(struct amdgpu_device *adev, u32 reg)
2418 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
2421 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
2425 static inline void si_pif_phy1_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
2429 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
2432 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
2434 static void si_program_aspm(struct amdgpu_device *adev)
2440 if (!amdgpu_device_should_use_aspm(adev))
2443 if (adev->flags & AMD_IS_APU)
2476 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2480 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2482 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2486 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2488 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2492 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2494 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2498 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2500 if ((adev->asic_type != CHIP_OLAND) && (adev->asic_type != CHIP_HAINAN)) {
2501 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_0);
2504 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_0, data);
2506 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_1);
2509 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_1, data);
2511 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_2);
2514 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_2, data);
2516 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_PWRDOWN_3);
2519 si_pif_phy0_wreg(adev,PB0_PIF_PWRDOWN_3, data);
2521 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_0);
2524 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_0, data);
2526 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_1);
2529 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_1, data);
2531 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_2);
2534 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_2, data);
2536 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_PWRDOWN_3);
2539 si_pif_phy1_wreg(adev,PB1_PIF_PWRDOWN_3, data);
2547 orig = data = si_pif_phy0_rreg(adev,PB0_PIF_CNTL);
2549 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
2552 si_pif_phy0_wreg(adev,PB0_PIF_CNTL, data);
2554 orig = data = si_pif_phy1_rreg(adev,PB1_PIF_CNTL);
2556 if ((adev->asic_type == CHIP_OLAND) || (adev->asic_type == CHIP_HAINAN))
2559 si_pif_phy1_wreg(adev,PB1_PIF_CNTL, data);
2562 !pci_is_root_bus(adev->pdev->bus)) {
2563 struct pci_dev *root = adev->pdev->bus->self;
2638 static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev)
2643 readrq = pcie_get_readrq(adev->pdev);
2646 pcie_set_readrq(adev->pdev, 512);
2651 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2653 si_fix_pci_max_read_req_size(adev);
2654 si_init_golden_registers(adev);
2655 si_pcie_gen3_enable(adev);
2656 si_program_aspm(adev);
2668 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2670 return si_common_hw_fini(adev);
2675 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2677 return si_common_hw_init(adev);
2733 int si_set_ip_blocks(struct amdgpu_device *adev)
2735 switch (adev->asic_type) {
2739 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2740 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2741 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2742 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2743 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2744 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2745 if (adev->enable_virtual_display)
2746 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2748 else if (amdgpu_device_has_dc_support(adev))
2749 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2752 amdgpu_device_ip_block_add(adev, &dce_v6_0_ip_block);
2753 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2754 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2757 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2758 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2759 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2760 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2761 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2762 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2763 if (adev->enable_virtual_display)
2764 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2766 else if (amdgpu_device_has_dc_support(adev))
2767 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2770 amdgpu_device_ip_block_add(adev, &dce_v6_4_ip_block);
2771 amdgpu_device_ip_block_add(adev, &uvd_v3_1_ip_block);
2772 /* amdgpu_device_ip_block_add(adev, &vce_v1_0_ip_block); */
2775 amdgpu_device_ip_block_add(adev, &si_common_ip_block);
2776 amdgpu_device_ip_block_add(adev, &gmc_v6_0_ip_block);
2777 amdgpu_device_ip_block_add(adev, &si_ih_ip_block);
2778 amdgpu_device_ip_block_add(adev, &gfx_v6_0_ip_block);
2779 amdgpu_device_ip_block_add(adev, &si_dma_ip_block);
2780 amdgpu_device_ip_block_add(adev, &si_smu_ip_block);
2781 if (adev->enable_virtual_display)
2782 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);