Lines Matching refs:adev
211 static int nv_query_video_codecs(struct amdgpu_device *adev, bool encode,
214 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
217 switch (adev->ip_versions[UVD_HWIP][0]) {
221 if (amdgpu_sriov_vf(adev)) {
222 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
234 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
279 static u32 nv_didt_rreg(struct amdgpu_device *adev, u32 reg)
287 spin_lock_irqsave(&adev->didt_idx_lock, flags);
290 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
294 static void nv_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
301 spin_lock_irqsave(&adev->didt_idx_lock, flags);
304 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
307 static u32 nv_get_config_memsize(struct amdgpu_device *adev)
309 return adev->nbio.funcs->get_memsize(adev);
312 static u32 nv_get_xclk(struct amdgpu_device *adev)
314 return adev->clock.spll.reference_freq;
318 void nv_grbm_select(struct amdgpu_device *adev,
330 static bool nv_read_disabled_bios(struct amdgpu_device *adev)
358 static uint32_t nv_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
363 mutex_lock(&adev->grbm_idx_mutex);
365 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
370 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
371 mutex_unlock(&adev->grbm_idx_mutex);
375 static uint32_t nv_get_register_value(struct amdgpu_device *adev,
380 return nv_read_indexed_register(adev, se_num, sh_num, reg_offset);
383 return adev->gfx.config.gb_addr_config;
388 static int nv_read_register(struct amdgpu_device *adev, u32 se_num,
397 if (!adev->reg_offset[en->hwip][en->inst])
399 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
403 *value = nv_get_register_value(adev,
411 static int nv_asic_mode2_reset(struct amdgpu_device *adev)
416 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
419 pci_clear_master(adev->pdev);
421 amdgpu_device_cache_pci_state(adev->pdev);
423 ret = amdgpu_dpm_mode2_reset(adev);
425 dev_err(adev->dev, "GPU mode2 reset failed\n");
427 amdgpu_device_load_pci_state(adev->pdev);
430 for (i = 0; i < adev->usec_timeout; i++) {
431 u32 memsize = adev->nbio.funcs->get_memsize(adev);
438 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
444 nv_asic_reset_method(struct amdgpu_device *adev)
453 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
456 switch (adev->ip_versions[MP1_HWIP][0]) {
469 if (amdgpu_dpm_is_baco_supported(adev))
476 static int nv_asic_reset(struct amdgpu_device *adev)
480 switch (nv_asic_reset_method(adev)) {
482 dev_info(adev->dev, "PCI reset\n");
483 ret = amdgpu_device_pci_reset(adev);
486 dev_info(adev->dev, "BACO reset\n");
487 ret = amdgpu_dpm_baco_reset(adev);
490 dev_info(adev->dev, "MODE2 reset\n");
491 ret = nv_asic_mode2_reset(adev);
494 dev_info(adev->dev, "MODE1 reset\n");
495 ret = amdgpu_device_mode1_reset(adev);
502 static int nv_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
508 static int nv_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
514 static void nv_program_aspm(struct amdgpu_device *adev)
516 if (!amdgpu_device_should_use_aspm(adev) || !amdgpu_device_aspm_support_quirk())
519 if (!(adev->flags & AMD_IS_APU) &&
520 (adev->nbio.funcs->program_aspm))
521 adev->nbio.funcs->program_aspm(adev);
533 void nv_set_virt_ops(struct amdgpu_device *adev)
535 adev->virt.ops = &xgpu_nv_virt_ops;
538 static bool nv_need_full_reset(struct amdgpu_device *adev)
543 static bool nv_need_reset_on_init(struct amdgpu_device *adev)
547 if (adev->flags & AMD_IS_APU)
560 static void nv_init_doorbell_index(struct amdgpu_device *adev)
562 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
563 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
564 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
565 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
566 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
567 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
568 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
569 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
570 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
571 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
572 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
573 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
574 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
575 adev->doorbell_index.gfx_userqueue_start =
577 adev->doorbell_index.gfx_userqueue_end =
579 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
580 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
581 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
582 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
583 adev->doorbell_index.sdma_engine[2] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE2;
584 adev->doorbell_index.sdma_engine[3] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE3;
585 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
586 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
587 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
588 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
589 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
590 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
591 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
593 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
594 adev->doorbell_index.sdma_doorbell_range = 20;
597 static void nv_pre_asic_init(struct amdgpu_device *adev)
601 static int nv_update_umd_stable_pstate(struct amdgpu_device *adev,
605 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
607 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
609 if (adev->gfx.funcs->update_perfmon_mgcg)
610 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
612 if (!(adev->flags & AMD_IS_APU) &&
613 (adev->nbio.funcs->enable_aspm) &&
614 amdgpu_device_should_use_aspm(adev))
615 adev->nbio.funcs->enable_aspm(adev, !enter);
643 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
645 if (!amdgpu_sriov_vf(adev)) {
646 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
647 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
649 adev->smc_rreg = NULL;
650 adev->smc_wreg = NULL;
651 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
652 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
653 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
654 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
655 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
656 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
659 adev->uvd_ctx_rreg = NULL;
660 adev->uvd_ctx_wreg = NULL;
662 adev->didt_rreg = &nv_didt_rreg;
663 adev->didt_wreg = &nv_didt_wreg;
665 adev->asic_funcs = &nv_asic_funcs;
667 adev->rev_id = amdgpu_device_get_rev_id(adev);
668 adev->external_rev_id = 0xff;
672 switch (adev->ip_versions[GC_HWIP][0]) {
674 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
689 adev->pg_flags = AMD_PG_SUPPORT_VCN |
693 adev->external_rev_id = adev->rev_id + 0x1;
696 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
711 adev->pg_flags = AMD_PG_SUPPORT_VCN |
714 adev->external_rev_id = adev->rev_id + 20;
717 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
733 adev->pg_flags = AMD_PG_SUPPORT_VCN |
741 if (amdgpu_sriov_vf(adev))
742 adev->rev_id = 0;
743 adev->external_rev_id = adev->rev_id + 0xa;
746 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
757 adev->pg_flags = AMD_PG_SUPPORT_VCN |
762 if (amdgpu_sriov_vf(adev)) {
764 adev->cg_flags = 0;
765 adev->pg_flags = 0;
767 adev->external_rev_id = adev->rev_id + 0x28;
770 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
781 adev->pg_flags = AMD_PG_SUPPORT_VCN |
786 adev->external_rev_id = adev->rev_id + 0x32;
789 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
804 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
808 if (adev->apu_flags & AMD_APU_IS_VANGOGH)
809 adev->external_rev_id = adev->rev_id + 0x01;
812 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
823 adev->pg_flags = AMD_PG_SUPPORT_VCN |
828 adev->external_rev_id = adev->rev_id + 0x3c;
831 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
841 adev->pg_flags = AMD_PG_SUPPORT_VCN |
845 adev->external_rev_id = adev->rev_id + 0x46;
848 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
868 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
872 if (adev->pdev->device == 0x1681)
873 adev->external_rev_id = 0x20;
875 adev->external_rev_id = adev->rev_id + 0x01;
879 adev->cg_flags = 0;
880 adev->pg_flags = 0;
881 adev->external_rev_id = adev->rev_id + 0x82;
884 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
903 adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
907 adev->external_rev_id = adev->rev_id + 0x01;
910 adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
930 adev->pg_flags = AMD_PG_SUPPORT_VCN |
934 adev->external_rev_id = adev->rev_id + 0x01;
941 if (adev->harvest_ip_mask & AMD_HARVEST_IP_VCN_MASK)
942 adev->pg_flags &= ~(AMD_PG_SUPPORT_VCN |
946 if (amdgpu_sriov_vf(adev)) {
947 amdgpu_virt_init_setting(adev);
948 xgpu_nv_mailbox_set_irq_funcs(adev);
956 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
958 if (amdgpu_sriov_vf(adev)) {
959 xgpu_nv_mailbox_get_irq(adev);
960 if (adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) {
961 amdgpu_virt_update_sriov_video_codec(adev,
967 amdgpu_virt_update_sriov_video_codec(adev,
978 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
985 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
987 if (amdgpu_sriov_vf(adev))
988 xgpu_nv_mailbox_add_irq_id(adev);
1000 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1002 if (adev->nbio.funcs->apply_lc_spc_mode_wa)
1003 adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
1005 if (adev->nbio.funcs->apply_l1_link_width_reconfig_wa)
1006 adev->nbio.funcs->apply_l1_link_width_reconfig_wa(adev);
1009 nv_program_aspm(adev);
1011 adev->nbio.funcs->init_registers(adev);
1016 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
1017 adev->nbio.funcs->remap_hdp_registers(adev);
1019 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
1026 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1033 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
1034 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
1041 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1043 return nv_common_hw_fini(adev);
1048 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1050 return nv_common_hw_init(adev);
1071 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1073 if (amdgpu_sriov_vf(adev))
1076 switch (adev->ip_versions[NBIO_HWIP][0]) {
1084 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
1086 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
1088 adev->hdp.funcs->update_clock_gating(adev,
1090 adev->smuio.funcs->update_rom_clock_gating(adev,
1108 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1110 if (amdgpu_sriov_vf(adev))
1113 adev->nbio.funcs->get_clockgating_state(adev, flags);
1115 adev->hdp.funcs->get_clock_gating_state(adev, flags);
1117 adev->smuio.funcs->get_clock_gating_state(adev, flags);