Lines Matching defs:data
1034 /* set index to data for continous read */
1702 u32 data, orig;
1716 orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1717 data &= ~PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS_MASK;
1718 data |= (0x24 << PCIE_LC_N_FTS_CNTL__LC_XMIT_N_FTS__SHIFT) |
1720 if (orig != data)
1721 WREG32_PCIE(ixPCIE_LC_N_FTS_CNTL, data);
1723 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3);
1724 data |= PCIE_LC_CNTL3__LC_GO_TO_RECOVERY_MASK;
1725 if (orig != data)
1726 WREG32_PCIE(ixPCIE_LC_CNTL3, data);
1728 orig = data = RREG32_PCIE(ixPCIE_P_CNTL);
1729 data |= PCIE_P_CNTL__P_IGNORE_EDB_ERR_MASK;
1730 if (orig != data)
1731 WREG32_PCIE(ixPCIE_P_CNTL, data);
1733 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1734 data &= ~(PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK |
1736 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1738 data |= (7 << PCIE_LC_CNTL__LC_L0S_INACTIVITY__SHIFT);
1741 data |= (7 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT);
1742 data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
1743 if (orig != data)
1744 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1749 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_0);
1750 data &= ~(PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1752 data |= (7 << PB0_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1754 if (orig != data)
1755 WREG32_PCIE(ixPB0_PIF_PWRDOWN_0, data);
1757 orig = data = RREG32_PCIE(ixPB0_PIF_PWRDOWN_1);
1758 data &= ~(PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1760 data |= (7 << PB0_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1762 if (orig != data)
1763 WREG32_PCIE(ixPB0_PIF_PWRDOWN_1, data);
1765 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_0);
1766 data &= ~(PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0_MASK |
1768 data |= (7 << PB1_PIF_PWRDOWN_0__PLL_POWER_STATE_IN_OFF_0__SHIFT) |
1770 if (orig != data)
1771 WREG32_PCIE(ixPB1_PIF_PWRDOWN_0, data);
1773 orig = data = RREG32_PCIE(ixPB1_PIF_PWRDOWN_1);
1774 data &= ~(PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1_MASK |
1776 data |= (7 << PB1_PIF_PWRDOWN_1__PLL_POWER_STATE_IN_OFF_1__SHIFT) |
1778 if (orig != data)
1779 WREG32_PCIE(ixPB1_PIF_PWRDOWN_1, data);
1781 orig = data = RREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL);
1782 data &= ~PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE_MASK;
1783 data |= ~(3 << PCIE_LC_LINK_WIDTH_CNTL__LC_DYN_LANES_PWR_STATE__SHIFT);
1784 if (orig != data)
1785 WREG32_PCIE(ixPCIE_LC_LINK_WIDTH_CNTL, data);
1800 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL2);
1801 data |= PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
1803 if (orig != data)
1804 WREG32_PCIE(ixPCIE_LC_CNTL2, data);
1806 orig = data = RREG32_SMC(ixTHM_CLK_CNTL);
1807 data &= ~(THM_CLK_CNTL__CMON_CLK_SEL_MASK |
1809 data |= (1 << THM_CLK_CNTL__CMON_CLK_SEL__SHIFT) |
1811 if (orig != data)
1812 WREG32_SMC(ixTHM_CLK_CNTL, data);
1814 orig = data = RREG32_SMC(ixMISC_CLK_CTRL);
1815 data &= ~(MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK |
1817 data |= (1 << MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT) |
1819 if (orig != data)
1820 WREG32_SMC(ixMISC_CLK_CTRL, data);
1822 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL);
1823 data &= ~CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK;
1824 if (orig != data)
1825 WREG32_SMC(ixCG_CLKPIN_CNTL, data);
1827 orig = data = RREG32_SMC(ixCG_CLKPIN_CNTL_2);
1828 data &= ~CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK;
1829 if (orig != data)
1830 WREG32_SMC(ixCG_CLKPIN_CNTL_2, data);
1832 orig = data = RREG32_SMC(ixMPLL_BYPASSCLK_SEL);
1833 data &= ~MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK;
1834 data |= (4 << MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT);
1835 if (orig != data)
1836 WREG32_SMC(ixMPLL_BYPASSCLK_SEL, data);
1840 if (orig != data)
1841 WREG32_PCIE(ixPCIE_LC_CNTL, data);
1844 orig = data = RREG32_PCIE(ixPCIE_CNTL2);
1845 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
1848 if (orig != data)
1849 WREG32_PCIE(ixPCIE_CNTL2, data);
1852 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL);
1853 if ((data & PCIE_LC_N_FTS_CNTL__LC_N_FTS_MASK) ==
1855 data = RREG32_PCIE(ixPCIE_LC_STATUS1);
1856 if ((data & PCIE_LC_STATUS1__LC_REVERSE_XMIT_MASK) &&
1857 (data & PCIE_LC_STATUS1__LC_REVERSE_RCVR_MASK)) {
1858 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL);
1859 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
1860 if (orig != data)
1861 WREG32_PCIE(ixPCIE_LC_CNTL, data);