Lines Matching defs:adev
130 static int cik_query_video_codecs(struct amdgpu_device *adev, bool encode,
133 switch (adev->asic_type) {
152 static u32 cik_pcie_rreg(struct amdgpu_device *adev, u32 reg)
157 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
161 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
165 static void cik_pcie_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
169 spin_lock_irqsave(&adev->pcie_idx_lock, flags);
174 spin_unlock_irqrestore(&adev->pcie_idx_lock, flags);
177 static u32 cik_smc_rreg(struct amdgpu_device *adev, u32 reg)
182 spin_lock_irqsave(&adev->smc_idx_lock, flags);
185 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
189 static void cik_smc_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
193 spin_lock_irqsave(&adev->smc_idx_lock, flags);
196 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
199 static u32 cik_uvd_ctx_rreg(struct amdgpu_device *adev, u32 reg)
204 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
207 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
211 static void cik_uvd_ctx_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
215 spin_lock_irqsave(&adev->uvd_ctx_idx_lock, flags);
218 spin_unlock_irqrestore(&adev->uvd_ctx_idx_lock, flags);
221 static u32 cik_didt_rreg(struct amdgpu_device *adev, u32 reg)
226 spin_lock_irqsave(&adev->didt_idx_lock, flags);
229 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
233 static void cik_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
237 spin_lock_irqsave(&adev->didt_idx_lock, flags);
240 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
827 static void cik_init_golden_registers(struct amdgpu_device *adev)
830 mutex_lock(&adev->grbm_idx_mutex);
832 switch (adev->asic_type) {
834 amdgpu_device_program_register_sequence(adev,
837 amdgpu_device_program_register_sequence(adev,
840 amdgpu_device_program_register_sequence(adev,
843 amdgpu_device_program_register_sequence(adev,
848 amdgpu_device_program_register_sequence(adev,
851 amdgpu_device_program_register_sequence(adev,
854 amdgpu_device_program_register_sequence(adev,
857 amdgpu_device_program_register_sequence(adev,
862 amdgpu_device_program_register_sequence(adev,
865 amdgpu_device_program_register_sequence(adev,
868 amdgpu_device_program_register_sequence(adev,
871 amdgpu_device_program_register_sequence(adev,
876 amdgpu_device_program_register_sequence(adev,
879 amdgpu_device_program_register_sequence(adev,
882 amdgpu_device_program_register_sequence(adev,
885 amdgpu_device_program_register_sequence(adev,
890 amdgpu_device_program_register_sequence(adev,
893 amdgpu_device_program_register_sequence(adev,
896 amdgpu_device_program_register_sequence(adev,
899 amdgpu_device_program_register_sequence(adev,
906 mutex_unlock(&adev->grbm_idx_mutex);
912 * @adev: amdgpu_device pointer
917 static u32 cik_get_xclk(struct amdgpu_device *adev)
919 u32 reference_clock = adev->clock.spll.reference_freq;
921 if (adev->flags & AMD_IS_APU) {
934 * @adev: amdgpu_device pointer
944 void cik_srbm_select(struct amdgpu_device *adev,
955 static void cik_vga_set_state(struct amdgpu_device *adev, bool state)
967 static bool cik_read_disabled_bios(struct amdgpu_device *adev)
977 if (adev->mode_info.num_crtc) {
986 if (adev->mode_info.num_crtc) {
999 r = amdgpu_read_bios(adev);
1003 if (adev->mode_info.num_crtc) {
1012 static bool cik_read_bios_from_rom(struct amdgpu_device *adev,
1024 if (adev->flags & AMD_IS_APU)
1030 spin_lock_irqsave(&adev->smc_idx_lock, flags);
1038 spin_unlock_irqrestore(&adev->smc_idx_lock, flags);
1122 static uint32_t cik_get_register_value(struct amdgpu_device *adev,
1133 return adev->gfx.config.rb_config[se_idx][sh_idx].rb_backend_disable;
1135 return adev->gfx.config.rb_config[se_idx][sh_idx].user_rb_backend_disable;
1137 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config;
1139 return adev->gfx.config.rb_config[se_idx][sh_idx].raster_config_1;
1142 mutex_lock(&adev->grbm_idx_mutex);
1144 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
1149 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
1150 mutex_unlock(&adev->grbm_idx_mutex);
1157 return adev->gfx.config.gb_addr_config;
1159 return adev->gfx.config.mc_arb_ramcfg;
1193 return adev->gfx.config.tile_mode_array[idx];
1211 return adev->gfx.config.macrotile_mode_array[idx];
1218 static int cik_read_register(struct amdgpu_device *adev, u32 se_num,
1230 *value = cik_get_register_value(adev, indexed, se_num, sh_num,
1243 static void kv_save_regs_for_reset(struct amdgpu_device *adev,
1257 static void kv_restore_regs_for_reset(struct amdgpu_device *adev,
1333 * @adev: amdgpu_device pointer
1339 static int cik_asic_pci_config_reset(struct amdgpu_device *adev)
1345 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1347 if (adev->flags & AMD_IS_APU)
1348 kv_save_regs_for_reset(adev, &kv_save);
1351 pci_clear_master(adev->pdev);
1353 amdgpu_device_pci_config_reset(adev);
1358 for (i = 0; i < adev->usec_timeout; i++) {
1361 pci_set_master(adev->pdev);
1362 adev->has_hw_reset = true;
1370 if (adev->flags & AMD_IS_APU)
1371 kv_restore_regs_for_reset(adev, &kv_save);
1373 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1378 static bool cik_asic_supports_baco(struct amdgpu_device *adev)
1380 switch (adev->asic_type) {
1383 return amdgpu_dpm_is_baco_supported(adev);
1390 cik_asic_reset_method(struct amdgpu_device *adev)
1399 dev_warn(adev->dev, "Specified reset:%d isn't supported, using AUTO instead.\n",
1402 switch (adev->asic_type) {
1405 baco_reset = cik_asic_supports_baco(adev);
1421 * @adev: amdgpu_device pointer
1427 static int cik_asic_reset(struct amdgpu_device *adev)
1432 if (adev->flags & AMD_IS_APU)
1435 if (cik_asic_reset_method(adev) == AMD_RESET_METHOD_BACO) {
1436 dev_info(adev->dev, "BACO reset\n");
1437 r = amdgpu_dpm_baco_reset(adev);
1439 dev_info(adev->dev, "PCI CONFIG reset\n");
1440 r = cik_asic_pci_config_reset(adev);
1446 static u32 cik_get_config_memsize(struct amdgpu_device *adev)
1451 static int cik_set_uvd_clock(struct amdgpu_device *adev, u32 clock,
1458 r = amdgpu_atombios_get_clock_dividers(adev,
1481 static int cik_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
1485 r = cik_set_uvd_clock(adev, vclk, ixCG_VCLK_CNTL, ixCG_VCLK_STATUS);
1489 r = cik_set_uvd_clock(adev, dclk, ixCG_DCLK_CNTL, ixCG_DCLK_STATUS);
1493 static int cik_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
1499 r = amdgpu_atombios_get_clock_dividers(adev,
1530 static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
1532 struct pci_dev *root = adev->pdev->bus->self;
1537 if (pci_is_root_bus(adev->pdev->bus))
1543 if (adev->flags & AMD_IS_APU)
1546 if (!(adev->pm.pcie_gen_mask & (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 |
1553 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1559 } else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2) {
1567 if (!pci_is_pcie(root) || !pci_is_pcie(adev->pdev))
1570 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3) {
1578 pcie_capability_set_word(adev->pdev, PCI_EXP_LNKCTL, PCI_EXP_LNKCTL_HAWD);
1602 pcie_capability_read_word(adev->pdev,
1610 pcie_capability_read_word(adev->pdev,
1616 pcie_capability_read_word(adev->pdev,
1635 pcie_capability_clear_and_set_word(adev->pdev, PCI_EXP_LNKCTL,
1652 pcie_capability_read_word(adev->pdev,
1660 pcie_capability_write_word(adev->pdev,
1677 pcie_capability_read_word(adev->pdev, PCI_EXP_LNKCTL2, &tmp16);
1680 if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1682 else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1686 pcie_capability_write_word(adev->pdev, PCI_EXP_LNKCTL2, tmp16);
1692 for (i = 0; i < adev->usec_timeout; i++) {
1700 static void cik_program_aspm(struct amdgpu_device *adev)
1706 if (!amdgpu_device_should_use_aspm(adev))
1709 if (pci_is_root_bus(adev->pdev->bus))
1713 if (adev->flags & AMD_IS_APU)
1788 struct pci_dev *root = adev->pdev->bus->self;
1867 static uint32_t cik_get_rev_id(struct amdgpu_device *adev)
1873 static void cik_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring)
1883 static void cik_invalidate_hdp(struct amdgpu_device *adev,
1894 static bool cik_need_full_reset(struct amdgpu_device *adev)
1900 static void cik_get_pcie_usage(struct amdgpu_device *adev, uint64_t *count0,
1910 if (adev->flags & AMD_IS_APU)
1946 static bool cik_need_reset_on_init(struct amdgpu_device *adev)
1950 if (adev->flags & AMD_IS_APU)
1963 static uint64_t cik_get_pcie_replay_count(struct amdgpu_device *adev)
1975 static void cik_pre_asic_init(struct amdgpu_device *adev)
2005 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2007 adev->smc_rreg = &cik_smc_rreg;
2008 adev->smc_wreg = &cik_smc_wreg;
2009 adev->pcie_rreg = &cik_pcie_rreg;
2010 adev->pcie_wreg = &cik_pcie_wreg;
2011 adev->uvd_ctx_rreg = &cik_uvd_ctx_rreg;
2012 adev->uvd_ctx_wreg = &cik_uvd_ctx_wreg;
2013 adev->didt_rreg = &cik_didt_rreg;
2014 adev->didt_wreg = &cik_didt_wreg;
2016 adev->asic_funcs = &cik_asic_funcs;
2018 adev->rev_id = cik_get_rev_id(adev);
2019 adev->external_rev_id = 0xFF;
2020 switch (adev->asic_type) {
2022 adev->cg_flags =
2039 adev->pg_flags = 0;
2040 adev->external_rev_id = adev->rev_id + 0x14;
2043 adev->cg_flags =
2059 adev->pg_flags = 0;
2060 adev->external_rev_id = 0x28;
2063 adev->cg_flags =
2078 adev->pg_flags =
2090 if (adev->pdev->device == 0x1312 ||
2091 adev->pdev->device == 0x1316 ||
2092 adev->pdev->device == 0x1317)
2093 adev->external_rev_id = 0x41;
2095 adev->external_rev_id = 0x1;
2099 adev->cg_flags =
2114 adev->pg_flags =
2124 if (adev->asic_type == CHIP_KABINI) {
2125 if (adev->rev_id == 0)
2126 adev->external_rev_id = 0x81;
2127 else if (adev->rev_id == 1)
2128 adev->external_rev_id = 0x82;
2129 else if (adev->rev_id == 2)
2130 adev->external_rev_id = 0x85;
2132 adev->external_rev_id = adev->rev_id + 0xa1;
2154 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2157 cik_init_golden_registers(adev);
2159 cik_pcie_gen3_enable(adev);
2161 cik_program_aspm(adev);
2173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2175 return cik_common_hw_fini(adev);
2180 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2182 return cik_common_hw_init(adev);
2239 int cik_set_ip_blocks(struct amdgpu_device *adev)
2241 switch (adev->asic_type) {
2243 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2244 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2245 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2246 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
2247 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2248 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2249 if (adev->enable_virtual_display)
2250 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2252 else if (amdgpu_device_has_dc_support(adev))
2253 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2256 amdgpu_device_ip_block_add(adev, &dce_v8_2_ip_block);
2257 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2258 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2261 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2262 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2263 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2264 amdgpu_device_ip_block_add(adev, &gfx_v7_3_ip_block);
2265 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2266 amdgpu_device_ip_block_add(adev, &pp_smu_ip_block);
2267 if (adev->enable_virtual_display)
2268 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2270 else if (amdgpu_device_has_dc_support(adev))
2271 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2274 amdgpu_device_ip_block_add(adev, &dce_v8_5_ip_block);
2275 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2276 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2279 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2280 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2281 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2282 amdgpu_device_ip_block_add(adev, &gfx_v7_1_ip_block);
2283 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2284 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
2285 if (adev->enable_virtual_display)
2286 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2288 else if (amdgpu_device_has_dc_support(adev))
2289 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2292 amdgpu_device_ip_block_add(adev, &dce_v8_1_ip_block);
2294 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2295 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);
2299 amdgpu_device_ip_block_add(adev, &cik_common_ip_block);
2300 amdgpu_device_ip_block_add(adev, &gmc_v7_0_ip_block);
2301 amdgpu_device_ip_block_add(adev, &cik_ih_ip_block);
2302 amdgpu_device_ip_block_add(adev, &gfx_v7_2_ip_block);
2303 amdgpu_device_ip_block_add(adev, &cik_sdma_ip_block);
2304 amdgpu_device_ip_block_add(adev, &kv_smu_ip_block);
2305 if (adev->enable_virtual_display)
2306 amdgpu_device_ip_block_add(adev, &amdgpu_vkms_ip_block);
2308 else if (amdgpu_device_has_dc_support(adev))
2309 amdgpu_device_ip_block_add(adev, &dm_ip_block);
2312 amdgpu_device_ip_block_add(adev, &dce_v8_3_ip_block);
2313 amdgpu_device_ip_block_add(adev, &uvd_v4_2_ip_block);
2314 amdgpu_device_ip_block_add(adev, &vce_v2_0_ip_block);