Lines Matching refs:reg
1122 uint32_t reg, uint32_t acc_flags);
1126 uint32_t reg, uint32_t v,
1131 uint32_t reg, uint32_t v, uint32_t xcc_id);
1163 #define RREG32_NO_KIQ(reg) amdgpu_device_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1164 #define WREG32_NO_KIQ(reg, v) amdgpu_device_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1166 #define RREG32_KIQ(reg) amdgpu_kiq_rreg(adev, (reg))
1167 #define WREG32_KIQ(reg, v) amdgpu_kiq_wreg(adev, (reg), (v))
1169 #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
1170 #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
1172 #define RREG32(reg) amdgpu_device_rreg(adev, (reg), 0)
1173 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_device_rreg(adev, (reg), 0))
1174 #define WREG32(reg, v) amdgpu_device_wreg(adev, (reg), (v), 0)
1177 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1178 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1179 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1180 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1181 #define RREG32_PCIE_EXT(reg) adev->pcie_rreg_ext(adev, (reg))
1182 #define WREG32_PCIE_EXT(reg, v) adev->pcie_wreg_ext(adev, (reg), (v))
1183 #define RREG64_PCIE(reg) adev->pcie_rreg64(adev, (reg))
1184 #define WREG64_PCIE(reg, v) adev->pcie_wreg64(adev, (reg), (v))
1185 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1186 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1187 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1188 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1189 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1190 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1191 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1192 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1193 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1194 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1195 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1196 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1197 #define WREG32_P(reg, val, mask) \
1199 uint32_t tmp_ = RREG32(reg); \
1202 WREG32(reg, tmp_); \
1204 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1205 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1206 #define WREG32_PLL_P(reg, val, mask) \
1208 uint32_t tmp_ = RREG32_PLL(reg); \
1211 WREG32_PLL(reg, tmp_); \
1222 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_device_rreg((adev), (reg), false))
1224 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1225 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1227 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1228 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1229 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1231 #define REG_GET_FIELD(value, reg, field) \
1232 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1234 #define WREG32_FIELD(reg, field, val) \
1235 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1237 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1238 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1327 u32 reg);
1329 u32 reg, u32 v);